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nvgpu: vgpu: add support to query rop_l2 en masks

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Fetch ROP_L2 enable masks in addition to other parameters
when guest sends command to query constants.

Bug 200401223

Change-Id: Ie386f24caaf7acd1155fc3f2a5e8c1f27016970a
Signed-off-by: Aparna Das <aparnad@nvidia.com>
(cherry picked from commit a08bb08fb9fff40138d26e5e9bfa21267ca6b6af)
Reviewed-on: https://git-master.nvidia.com/r/1694911
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Aparna Das
2018-04-05 19:20:40 -07:00
committed by mobile promotions
parent d0e4dfd6ef
commit 31024f85eb
2 changed files with 22 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
View File

@@ -455,6 +455,7 @@ struct tegra_vgpu_engines_info {
#define TEGRA_VGPU_MAX_GPC_COUNT 16
#define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16
#define TEGRA_VGPU_L2_EN_MASK 32
struct tegra_vgpu_constants_params {
u32 arch;
@@ -494,6 +495,7 @@ struct tegra_vgpu_constants_params {
u32 num_pce;
u32 sm_per_tpc;
u32 max_subctx_count;
u32 l2_en_mask[TEGRA_VGPU_L2_EN_MASK];
};
struct tegra_vgpu_channel_cyclestats_snapshot_params {

22
drivers/gpu/nvgpu/vgpu/gr_vgpu.c
View File

@@ -746,8 +746,23 @@ u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g)
u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g)
{
/* no one use it yet */
return NULL;
struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
u32 i, max_fbps_count = priv->constants.num_fbps;
gk20a_dbg_fn("");
if (g->gr.fbp_rop_l2_en_mask == NULL) {
g->gr.fbp_rop_l2_en_mask =
nvgpu_kzalloc(g, max_fbps_count * sizeof(u32));
if (!g->gr.fbp_rop_l2_en_mask)
return NULL;
}
g->gr.max_fbps_count = max_fbps_count;
for (i = 0; i < max_fbps_count; i++)
g->gr.fbp_rop_l2_en_mask[i] = priv->constants.l2_en_mask[i];
return g->gr.fbp_rop_l2_en_mask;
}
int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
@@ -840,6 +855,9 @@ static void vgpu_remove_gr_support(struct gr_gk20a *gr)
nvgpu_kfree(gr->g, gr->gpc_tpc_count);
gr->gpc_tpc_count = NULL;
nvgpu_kfree(gr->g, gr->fbp_rop_l2_en_mask);
gr->fbp_rop_l2_en_mask = NULL;
}
static int vgpu_gr_init_gr_setup_sw(struct gk20a *g)