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gpu: nvgpu: Add a new device manager unit

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This adds a new device management unit in the common code responsible
for facilitating the parsing of the GPU top device list and providing
that info to other units in nvgpu.

The basic idea is to read this list once from HW and store it in a
set of lists corresponding to each device type (graphics, LCE, etc).
Many of the HALs in top can be deleted and instead implemented using
common code parsing the SW representation.

Every time the driver queries the device list it does so using a
device type and instance ID. This is common code. The HAL is responsible
for populating the device list in such a way that the driver can
query it in a chip agnostic manner.

Also delete some of the unit tests for functions that no longer
exist. This code will require new unit tests in time; those should be
quite simple to write once unit testing is needed.

JIRA NVGPU-5421

Change-Id: Ie41cd255404b90ae0376098a2d6e9f9abdd3f5ea
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319649
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2020-03-27 14:36:24 -06:00
parent f6298157bc
commit 319520ff57
33 changed files with 631 additions and 898 deletions
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52
userspace/units/fifo/engine/nvgpu-engine.c
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@@ -177,13 +177,6 @@ done:
#define F_ENGINE_INIT_INFO_INIT_CE_FAIL BIT(3)
#define F_ENGINE_INIT_INFO_LAST BIT(4)
static int stub_top_get_device_info_EINVAL(struct gk20a *g,
struct nvgpu_device_info *dev_info,
u32 engine_type, u32 inst_id)
{
return -EINVAL;
}
static bool stub_pbdma_find_for_runlist_none(struct gk20a *g,
u32 runlist_id, u32 *pbdma_id)
{
@@ -228,15 +221,6 @@ int test_engine_init_info(struct unit_module *m,
unit_verbose(m, "%s branches=%s\n", __func__,
branches_str(branches, labels));
if (branches & F_ENGINE_INIT_INFO_GET_DEV_INFO_NULL) {
g->ops.top.get_device_info = NULL;
} else {
g->ops.top.get_device_info =
branches & F_ENGINE_INIT_INFO_GET_DEV_INFO_FAIL ?
stub_top_get_device_info_EINVAL :
gops.top.get_device_info;
}
g->ops.pbdma.find_for_runlist =
branches & F_ENGINE_INIT_INFO_PBDMA_FIND_FAIL ?
stub_pbdma_find_for_runlist_none :
@@ -445,41 +429,6 @@ done:
return ret;
}
int test_engine_enum_from_type(struct unit_module *m,
struct gk20a *g, void *args)
{
int ret = UNIT_FAIL;
int engine_enum;
struct gpu_ops gops = g->ops;
engine_enum = nvgpu_engine_enum_from_type(g,
top_device_info_type_enum_graphics_v());
unit_assert(engine_enum == NVGPU_ENGINE_GR, goto done);
engine_enum = nvgpu_engine_enum_from_type(g,
top_device_info_type_enum_lce_v());
unit_assert(engine_enum == NVGPU_ENGINE_ASYNC_CE, goto done);
engine_enum = nvgpu_engine_enum_from_type(g, 0xff);
unit_assert(engine_enum == NVGPU_ENGINE_INVAL, goto done);
g->ops.top.is_engine_gr = NULL;
engine_enum = nvgpu_engine_enum_from_type(g,
top_device_info_type_enum_graphics_v());
unit_assert(engine_enum == NVGPU_ENGINE_INVAL, goto done);
g->ops = gops;
g->ops.top.is_engine_ce = NULL;
engine_enum = nvgpu_engine_enum_from_type(g,
top_device_info_type_enum_graphics_v());
unit_assert(engine_enum == NVGPU_ENGINE_INVAL, goto done);
ret = UNIT_SUCCESS;
done:
g->ops = gops;
return ret;
}
int test_engine_interrupt_mask(struct unit_module *m,
struct gk20a *g, void *args)
{
@@ -980,7 +929,6 @@ struct unit_module_test nvgpu_engine_tests[] = {
UNIT_TEST(init_info, test_engine_init_info, &u, 0),
UNIT_TEST(ids, test_engine_ids, &u, 0),
UNIT_TEST(get_active_eng_info, test_engine_get_active_eng_info, &u, 0),
UNIT_TEST(enum_from_type, test_engine_enum_from_type, &u, 0),
UNIT_TEST(interrupt_mask, test_engine_interrupt_mask, &u, 0),
UNIT_TEST(get_fast_ce_runlist_id,
test_engine_get_fast_ce_runlist_id, &u, 0),