gpu: nvgpu: gv11b: Set pbdma, fb and ctxsw timeout for pre-si

fb and ctxsw timeout detection should be disabled for simulation
architectures. Also set timeouts to max for pbdma, fb and
ctxsw timeouts.

Bug 200289427

Change-Id: I8723d5ee9ea2535f401b1972c8c14ffab8f9504a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549522
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -1166,10 +1166,27 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
 
 	timeout = gk20a_readl(g, fifo_fb_timeout_r());
 	nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout);
+	if (!nvgpu_platform_is_silicon(g)) {
+		timeout = set_field(timeout, fifo_fb_timeout_period_m(),
+					fifo_fb_timeout_period_max_f());
+		timeout = set_field(timeout, fifo_fb_timeout_detection_m(),
+					fifo_fb_timeout_detection_disabled_f());
+		nvgpu_log_info(g, "new fifo_fb_timeout reg val = 0x%08x",
+					timeout);
+		gk20a_writel(g, fifo_fb_timeout_r(), timeout);
+	}
+
 	for (i = 0; i < host_num_pbdma; i++) {
 		timeout = gk20a_readl(g, pbdma_timeout_r(i));
 		nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x",
 						 timeout);
+		if (!nvgpu_platform_is_silicon(g)) {
+			timeout = set_field(timeout, pbdma_timeout_period_m(),
+					pbdma_timeout_period_max_f());
+			nvgpu_log_info(g, "new pbdma_timeout reg val = 0x%08x",
+						 timeout);
+			gk20a_writel(g, pbdma_timeout_r(i), timeout);
+		}
 	}
 
 	/* clear and enable pbdma interrupt */
@@ -1189,12 +1206,26 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g)
 	/* clear ctxsw timeout interrupts */
 	gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ~0);
 
+	if (nvgpu_platform_is_silicon(g)) {
 		/* enable ctxsw timeout */
 		timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US;
 		timeout = scale_ptimer(timeout,
 			ptimer_scalingfactor10x(g->ptimer_src_freq));
 		timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f();
 		gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout);
+	} else {
+		timeout = gk20a_readl(g, fifo_eng_ctxsw_timeout_r());
+		nvgpu_log_info(g, "fifo_eng_ctxsw_timeout reg val = 0x%08x",
+						 timeout);
+		timeout = set_field(timeout, fifo_eng_ctxsw_timeout_period_m(),
+				fifo_eng_ctxsw_timeout_period_max_f());
+		timeout = set_field(timeout,
+				fifo_eng_ctxsw_timeout_detection_m(),
+				fifo_eng_ctxsw_timeout_detection_disabled_f());
+		nvgpu_log_info(g, "new fifo_eng_ctxsw_timeout reg val = 0x%08x",
+						 timeout);
+		gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout);
+	}
 
 	/* clear runlist interrupts */
 	gk20a_writel(g, fifo_intr_runlist_r(), ~0);

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h

@@ -382,6 +382,18 @@ static inline u32 fifo_fb_timeout_period_init_f(void)
 {
 	return 0x3c00;
 }
+static inline u32 fifo_fb_timeout_detection_m(void)
+{
+	return 0x1 << 31;
+}
+static inline u32 fifo_fb_timeout_detection_enabled_f(void)
+{
+	return 0x80000000;
+}
+static inline u32 fifo_fb_timeout_detection_disabled_f(void)
+{
+	return 0x0;
+}
 static inline u32 fifo_sched_disable_r(void)
 {
 	return 0x00002630;
@@ -538,18 +550,38 @@ static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v)
 {
 	return (v & 0x7fffffff) << 0;
 }
+static inline u32 fifo_eng_ctxsw_timeout_period_m(void)
+{
+	return 0x7fffffff << 0;
+}
 static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r)
 {
 	return (r >> 0) & 0x7fffffff;
 }
+static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void)
+{
+	return 0x3fffff;
+}
+static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void)
+{
+	return 0x7fffffff;
+}
 static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v)
 {
 	return (v & 0x1) << 31;
 }
+static inline u32 fifo_eng_ctxsw_timeout_detection_m(void)
+{
+	return 0x1 << 31;
+}
 static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void)
+{
+	return 0x0;
+}
 static inline u32 fifo_pbdma_status_r(u32 i)
 {
 	return 0x00003080 + i*4;