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gpu: nvgpu: add tsg_verify_status_faulted operation

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Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as
g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100

This API will check if channel has ENG_FAULTED status set, if yes it will clear
CE method buffer in case saved out channel is same as faulted channel
We need to write 0 to method count to invalidate CE method buffer

Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100

Bug 200327095

Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2017-09-14 05:48:07 -07:00
committed by mobile promotions
parent 52f50addc6
commit f720b309f1
6 changed files with 65 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -399,6 +399,8 @@ static const struct gpu_ops gv100_ops = {
.preempt_tsg = gv11b_fifo_preempt_tsg,
.enable_tsg = gv11b_fifo_enable_tsg,
.disable_tsg = gk20a_disable_tsg,
.tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
.tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted,
.update_runlist = gk20a_fifo_update_runlist,
.trigger_mmu_fault = NULL,
.get_mmu_fault_info = NULL,

35
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -1811,3 +1811,38 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
else
*pbdma_id = FIFO_INVAL_PBDMA_ID;
}
static bool gk20a_fifo_channel_status_is_eng_faulted(struct gk20a *g, u32 chid)
{
u32 channel = gk20a_readl(g, ccsr_channel_r(chid));
return ccsr_channel_eng_faulted_v(channel) ==
ccsr_channel_eng_faulted_true_v();
}
void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch)
{
struct gk20a *g = ch->g;
struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
/*
* If channel has FAULTED set, clear the CE method buffer
* if saved out channel is same as faulted channel
*/
if (!gk20a_fifo_channel_status_is_eng_faulted(g, ch->chid))
return;
if (tsg->eng_method_buffers == NULL)
return;
/*
* CE method buffer format :
* DWord0 = method count
* DWord1 = channel id
*
* It is sufficient to write 0 to method count to invalidate
*/
if ((u32)ch->chid ==
nvgpu_mem_rd32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 1))
nvgpu_mem_wr32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 0, 0);
}

2
drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
View File

@@ -103,4 +103,6 @@ void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g,
u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd);
int gv11b_init_fifo_setup_hw(struct gk20a *g);
void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch);
#endif

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -432,6 +432,8 @@ static const struct gpu_ops gv11b_ops = {
.preempt_tsg = gv11b_fifo_preempt_tsg,
.enable_tsg = gv11b_fifo_enable_tsg,
.disable_tsg = gk20a_disable_tsg,
.tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
.tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted,
.update_runlist = gk20a_fifo_update_runlist,
.trigger_mmu_fault = NULL,
.get_mmu_fault_info = NULL,

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
View File

@@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void)
{
return 0x00000001;
}
static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
{
return 0x100;
}
static inline u32 ccsr_channel_pbdma_faulted_f(u32 v)
{
return (v & 0x1) << 22;
@@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v)
{
return (v & 0x1) << 23;
}
static inline u32 ccsr_channel_eng_faulted_v(u32 r)
{
return (r >> 23) & 0x1;
}
static inline u32 ccsr_channel_eng_faulted_reset_f(void)
{
return 0x800000;
}
static inline u32 ccsr_channel_eng_faulted_true_v(void)
{
return 0x00000001;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28) & 0x1;

12
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h
View File

@@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void)
{
return 0x00000001;
}
static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
{
return 0x100;
}
static inline u32 ccsr_channel_pbdma_faulted_f(u32 v)
{
return (v & 0x1) << 22;
@@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v)
{
return (v & 0x1) << 23;
}
static inline u32 ccsr_channel_eng_faulted_v(u32 r)
{
return (r >> 23) & 0x1;
}
static inline u32 ccsr_channel_eng_faulted_reset_f(void)
{
return 0x800000;
}
static inline u32 ccsr_channel_eng_faulted_true_v(void)
{
return 0x00000001;
}
static inline u32 ccsr_channel_busy_v(u32 r)
{
return (r >> 28) & 0x1;