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gpu: nvgpu: gp10b: sim: handle priv ring interrupts

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priv_ring interrupts are enabled for sim. Handle the
interrupt on sim too.

JIRA NVGPU-4864
JIRA NVGPU-5017

Change-Id: I2ff16c0a8ff152839765556dd3b117995f9de109
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306040
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Seema Khowala
2020-03-02 14:42:46 -08:00
committed by Alex Waterman
parent 20a4080be0
commit 31b8ecbcee
1 changed files with 1 additions and 8 deletions
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9
drivers/gpu/nvgpu/hal/priv_ring/priv_ring_gp10b_fusa.c
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@@ -1,7 +1,7 @@
/*
* GP10B priv ring
*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -211,13 +211,6 @@ void gp10b_priv_ring_isr(struct gk20a *g)
u32 cmd;
s32 retry;
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
nvgpu_info(g, "unhandled priv ring intr");
return;
}
#endif
status0 = nvgpu_readl(g, pri_ringmaster_intr_status0_r());
status1 = nvgpu_readl(g, pri_ringmaster_intr_status1_r());