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gpu: nvgpu: gr.intr MISRA fixes for Rule 16.x

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Fix MISRA Rule 16.x violations in gr.intr unit
All statements to be well-formed with terminating break statement for
every switch-clause.

Jira NVGPU-3395

Change-Id: Iad3a29628f44dfe64cfe916b5a8007a679c2fdc7
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114160
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-05-07 16:41:32 -07:00
committed by mobile promotions
parent efe34ec6d7
commit 31c8f09241
4 changed files with 44 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.c
View File

@@ -39,6 +39,8 @@
int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data) u32 class_num, u32 offset, u32 data)
{ {
int ret = 0;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
if (class_num == MAXWELL_COMPUTE_B) { if (class_num == MAXWELL_COMPUTE_B) {
@@ -50,10 +52,15 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
g->ops.gr.init.lg_coalesce(g, data); g->ops.gr.init.lg_coalesce(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
if (ret != 0) {
goto fail;
}
if (class_num == MAXWELL_B) { if (class_num == MAXWELL_B) {
switch (offset << 2) { switch (offset << 2) {
case NVB197_SET_SHADER_EXCEPTIONS: case NVB197_SET_SHADER_EXCEPTIONS:
@@ -69,13 +76,13 @@ int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
g->ops.gr.init.lg_coalesce(g, data); g->ops.gr.init.lg_coalesce(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
return 0;
fail: fail:
return -EINVAL; return ret;
} }
void gm20b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data) void gm20b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)

15
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.c
View File

@@ -194,6 +194,8 @@ void gp10b_gr_intr_set_coalesce_buffer_size(struct gk20a *g, u32 data)
int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data) u32 class_num, u32 offset, u32 data)
{ {
int ret = 0;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
if (class_num == PASCAL_COMPUTE_A) { if (class_num == PASCAL_COMPUTE_A) {
@@ -205,10 +207,15 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
g->ops.gr.init.lg_coalesce(g, data); g->ops.gr.init.lg_coalesce(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
if (ret != 0) {
goto fail;
}
if (class_num == PASCAL_A) { if (class_num == PASCAL_A) {
switch (offset << 2) { switch (offset << 2) {
case NVC097_SET_SHADER_EXCEPTIONS: case NVC097_SET_SHADER_EXCEPTIONS:
@@ -236,13 +243,13 @@ int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
g->ops.gr.set_bes_crop_debug4(g, data); g->ops.gr.set_bes_crop_debug4(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
return 0;
fail: fail:
return -EINVAL; return ret;
} }
static void gr_gp10b_sm_lrf_ecc_overcount_war(bool single_err, static void gr_gp10b_sm_lrf_ecc_overcount_war(bool single_err,

15
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
View File

@@ -172,6 +172,8 @@ void gv11b_gr_intr_set_shader_cut_collector(struct gk20a *g, u32 data)
int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data) u32 class_num, u32 offset, u32 data)
{ {
int ret = 0;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
if (class_num == VOLTA_COMPUTE_A) { if (class_num == VOLTA_COMPUTE_A) {
@@ -186,10 +188,15 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
gv11b_gr_intr_set_shader_cut_collector(g, data); gv11b_gr_intr_set_shader_cut_collector(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
if (ret != 0) {
goto fail;
}
if (class_num == VOLTA_A) { if (class_num == VOLTA_A) {
switch (offset << 2) { switch (offset << 2) {
case NVC397_SET_SHADER_EXCEPTIONS: case NVC397_SET_SHADER_EXCEPTIONS:
@@ -223,13 +230,13 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
gv11b_gr_intr_set_shader_cut_collector(g, data); gv11b_gr_intr_set_shader_cut_collector(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
return 0;
fail: fail:
return -EINVAL; return ret;
} }
void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data) void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)

15
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
View File

@@ -62,6 +62,8 @@ static void gr_tu104_set_sm_disp_ctrl(struct gk20a *g, u32 data)
int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr, int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data) u32 class_num, u32 offset, u32 data)
{ {
int ret = 0;
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
if (class_num == TURING_COMPUTE_A) { if (class_num == TURING_COMPUTE_A) {
@@ -79,10 +81,15 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
gv11b_gr_intr_set_shader_cut_collector(g, data); gv11b_gr_intr_set_shader_cut_collector(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
if (ret != 0) {
goto fail;
}
if (class_num == TURING_A) { if (class_num == TURING_A) {
switch (offset << 2) { switch (offset << 2) {
case NVC597_SET_SHADER_EXCEPTIONS: case NVC597_SET_SHADER_EXCEPTIONS:
@@ -119,13 +126,13 @@ int tu104_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
gv11b_gr_intr_set_shader_cut_collector(g, data); gv11b_gr_intr_set_shader_cut_collector(g, data);
break; break;
default: default:
goto fail; ret = -EINVAL;
break;
} }
} }
return 0;
fail: fail:
return -EINVAL; return ret;
} }
void tu104_gr_intr_enable_gpc_exceptions(struct gk20a *g, void tu104_gr_intr_enable_gpc_exceptions(struct gk20a *g,