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gpu: nvgpu: use correct APIs for disable and preempt
In gr_gk20a_ctx_zcull_setup(), gr_gk20a_update_smpc_ctxsw_mode(), and in gk20a_channel_suspend(), we call channel specific APIs to disable/preempt/enable channel But we do not consider TSGs in this case Hence use correct (below) APIs in above functions which will handle channel or TSG internally : gk20a_disable_channel_tsg() gk20a_fifo_preempt() gk20a_enable_channel_tsg() Bug 200205041 Change-Id: Ieed378dac4ad2322b35f9102706176ec326d386c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157189 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
committed by
Terje Bergstrom
parent
9d13ddc17d
commit
31fa6773ef
@@ -2772,9 +2772,9 @@ int gk20a_channel_suspend(struct gk20a *g)
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if (gk20a_channel_get(ch)) {
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gk20a_dbg_info("suspend channel %d", chid);
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/* disable channel */
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g->ops.fifo.disable_channel(ch);
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gk20a_disable_channel_tsg(g, ch);
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/* preempt the channel */
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g->ops.fifo.preempt_channel(g, chid);
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gk20a_fifo_preempt(g, ch);
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gk20a_channel_cancel_job_clean_up(ch, true);
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/* wait for channel update notifiers */
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if (ch->update_fn)
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@@ -764,12 +764,15 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c)
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va_hi = u64_hi32(ch_ctx->zcull_ctx.gpu_va);
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va = ((va_lo >> 8) & 0x00FFFFFF) | ((va_hi << 24) & 0xFF000000);
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c->g->ops.fifo.disable_channel(c);
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ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid);
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ret = gk20a_disable_channel_tsg(g, c);
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if (ret) {
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c->g->ops.fifo.enable_channel(c);
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gk20a_err(dev_from_gk20a(g),
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"failed to disable gr engine activity\n");
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gk20a_err(dev_from_gk20a(g), "failed to disable channel/TSG\n");
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goto clean_up;
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}
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ret = gk20a_fifo_preempt(g, c);
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if (ret) {
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gk20a_enable_channel_tsg(g, c);
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gk20a_err(dev_from_gk20a(g), "failed to preempt channel/TSG\n");
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goto clean_up;
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}
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@@ -780,7 +783,7 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c)
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gk20a_mem_wr(g, mem,
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ctxsw_prog_main_image_zcull_ptr_o(), va);
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c->g->ops.fifo.enable_channel(c);
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gk20a_enable_channel_tsg(g, c);
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clean_up:
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gk20a_mem_end(g, mem);
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@@ -1617,10 +1620,15 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
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mem = &ch_ctx->gr_ctx->mem;
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c->g->ops.fifo.disable_channel(c);
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ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid);
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ret = gk20a_disable_channel_tsg(g, c);
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if (ret) {
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gk20a_err(dev_from_gk20a(g), "failed to preempt channel");
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gk20a_err(dev_from_gk20a(g), "failed to disable channel/TSG\n");
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goto out;
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}
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ret = gk20a_fifo_preempt(g, c);
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if (ret) {
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gk20a_enable_channel_tsg(g, c);
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gk20a_err(dev_from_gk20a(g), "failed to preempt channel/TSG\n");
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goto out;
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}
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@@ -1646,7 +1654,7 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
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gk20a_mem_end(g, mem);
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out:
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c->g->ops.fifo.enable_channel(c);
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gk20a_enable_channel_tsg(g, c);
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return ret;
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}
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