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gpu: nvgpu: initialze bundle64 state

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We receive bundle with address and 64 bit values from ucode on some platforms
This patch adds the support to handle 64 bit values

Add struct av64_gk20a to store an address and corresponding 64 bit value
Add struct av64_list_gk20a to store count and list of av64_gk20a

Add API alloc_av64_list_gk20a() to allocate the list that supports 64bit
values

In gr_gk20a_init_ctx_vars_fw(), if we see NETLIST_REGIONID_SW_BUNDLE64_INIT,
load the bundle64 state into above local structures

Add new HAL gops.gr.init_sw_bundle64() and call it from gk20a_init_sw_bundle()
if defined

Also load the bundle for simulation cases in gr_gk20a_init_ctx_vars_sim()

Jira NVGPUT-96

Change-Id: I1ab7fb37ff91c5fbd968c93d714725b01fd4f59b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1736450
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-05-31 15:33:50 -07:00
committed by Tejal Kudav
parent 85b920442a
commit 328a7bd3ff
6 changed files with 61 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -475,6 +475,7 @@ struct gpu_ops {
u32 *priv_addr_table,
u32 *priv_addr_table_index);
u32 (*fecs_ctxsw_mailbox_size)(void);
int (*init_sw_bundle64)(struct gk20a *g);
} gr;
struct {
void (*init_hw)(struct gk20a *g);

21
drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
View File

@@ -57,6 +57,18 @@ static int gr_gk20a_alloc_load_netlist_av(struct gk20a *g, u32 *src, u32 len,
return 0;
}
static int gr_gk20a_alloc_load_netlist_av64(struct gk20a *g, u32 *src, u32 len,
struct av64_list_gk20a *av64_list)
{
av64_list->count = len / sizeof(struct av64_gk20a);
if (!alloc_av64_list_gk20a(g, av64_list))
return -ENOMEM;
memcpy(av64_list->l, src, len);
return 0;
}
static int gr_gk20a_alloc_load_netlist_aiv(struct gk20a *g, u32 *src, u32 len,
struct aiv_list_gk20a *aiv_list)
{
@@ -343,6 +355,14 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr)
if (err)
goto clean_up;
break;
case NETLIST_REGIONID_SW_BUNDLE64_INIT:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_BUNDLE64_INIT");
err = gr_gk20a_alloc_load_netlist_av64(g,
src, size,
&g->gr.ctx_vars.sw_bundle64_init);
if (err)
goto clean_up;
break;
case NETLIST_REGIONID_NVPERF_PMCAU:
nvgpu_log_info(g, "NETLIST_REGIONID_NVPERF_PMCAU");
err = gr_gk20a_alloc_load_netlist_aiv(g,
@@ -403,6 +423,7 @@ clean_up:
nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_rop.l);
nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_ucgpc.l);
nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.etpc.l);
nvgpu_kfree(g, g->gr.ctx_vars.sw_bundle64_init.l);
nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_cau.l);
nvgpu_release_firmware(g, netlist_fw);
err = -ENOENT;

17
drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
View File

@@ -105,6 +105,7 @@ union __max_name {
#define NETLIST_REGIONID_CTXREG_PMROP 31
#define NETLIST_REGIONID_CTXREG_PMUCGPC 32
#define NETLIST_REGIONID_CTXREG_ETPC 33
#define NETLIST_REGIONID_SW_BUNDLE64_INIT 34
#define NETLIST_REGIONID_NVPERF_PMCAU 35
struct netlist_region {
@@ -127,6 +128,11 @@ struct av_gk20a {
u32 addr;
u32 value;
};
struct av64_gk20a {
u32 addr;
u32 value_lo;
u32 value_hi;
};
struct aiv_gk20a {
u32 addr;
u32 index;
@@ -140,6 +146,10 @@ struct av_list_gk20a {
struct av_gk20a *l;
u32 count;
};
struct av64_list_gk20a {
struct av64_gk20a *l;
u32 count;
};
struct u32_list_gk20a {
u32 *l;
u32 count;
@@ -157,6 +167,13 @@ struct av_gk20a *alloc_av_list_gk20a(struct gk20a *g, struct av_list_gk20a *avl)
return avl->l;
}
static inline
struct av64_gk20a *alloc_av64_list_gk20a(struct gk20a *g, struct av64_list_gk20a *avl)
{
avl->l = nvgpu_kzalloc(g, avl->count * sizeof(*avl->l));
return avl->l;
}
static inline
struct aiv_gk20a *alloc_aiv_list_gk20a(struct gk20a *g,
struct aiv_list_gk20a *aivl)

14
drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
View File

@@ -63,6 +63,8 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
&g->gr.ctx_vars.sw_ctx_load.count);
g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0,
&g->gr.ctx_vars.sw_veid_bundle_init.count);
g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT_SIZE", 0,
&g->gr.ctx_vars.sw_bundle64_init.count);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0,
&g->gr.ctx_vars.sw_non_ctx_load.count);
@@ -92,6 +94,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.inst);
err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.gpccs.data);
err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_bundle_init);
err |= !alloc_av64_list_gk20a(g, &g->gr.ctx_vars.sw_bundle64_init);
err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_method_init);
err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.sw_ctx_load);
err |= !alloc_av_list_gk20a(g, &g->gr.ctx_vars.sw_non_ctx_load);
@@ -168,6 +171,17 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
i, &l[i].value);
}
for (i = 0; i < g->gr.ctx_vars.sw_bundle64_init.count; i++) {
struct av64_gk20a *l = g->gr.ctx_vars.sw_bundle64_init.l;
g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:VALUE_LO",
i, &l[i].value_lo);
g->sim->esc_readl(g, "GRCTX_SW_BUNDLE64_INIT:VALUE_HI",
i, &l[i].value_hi);
}
for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",

7
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1373,6 +1373,12 @@ u32 gk20a_init_sw_bundle(struct gk20a *g)
goto error;
}
if (g->ops.gr.init_sw_bundle64) {
err = g->ops.gr.init_sw_bundle64(g);
if (err)
goto error;
}
/* disable pipe mode override */
gk20a_writel(g, gr_pipe_bundle_config_r(),
gr_pipe_bundle_config_override_pipe_mode_disabled_f());
@@ -3130,6 +3136,7 @@ static void gk20a_remove_gr_support(struct gr_gk20a *gr)
nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.gpc_router.l);
nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.pm_ltc.l);
nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.pm_fbpa.l);
nvgpu_kfree(g, gr->ctx_vars.sw_bundle64_init.l);
nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.pm_cau.l);
nvgpu_vfree(g, gr->ctx_vars.local_golden_image);

1
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -297,6 +297,7 @@ struct gr_gk20a {
struct aiv_list_gk20a sw_ctx_load;
struct av_list_gk20a sw_non_ctx_load;
struct av_list_gk20a sw_veid_bundle_init;
struct av64_list_gk20a sw_bundle64_init;
struct {
struct aiv_list_gk20a sys;
struct aiv_list_gk20a gpc;