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gpu: nvgpu: add HAL for reading gcplex fuse

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This adds a HAL interface for reading the gcplex fuse and sets up the
HAL for the appropriate devices.

JIRA NVGPU-938

Change-Id: I83ed8b78b70f5b24ac3921d174c299abc91e286d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945141
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2018-11-07 13:04:30 -05:00
committed by mobile promotions
parent e156066256
commit 328fcb4c76
7 changed files with 15 additions and 4 deletions
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2
drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
View File

@@ -45,7 +45,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
return 0;
}
if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config) != 0) {
if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) {
nvgpu_err(g, "err reading gcplex config fuse, check fuse clk");
return -EINVAL;
}

2
drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
View File

@@ -46,7 +46,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
return 0;
}
if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config) != 0) {
if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) {
nvgpu_err(g, "err reading gcplex config fuse, check fuse clk");
return -EINVAL;
}

5
drivers/gpu/nvgpu/common/pmu/pmu_gm20b.c
View File

@@ -267,8 +267,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g)
g->ops.fuse.fuse_opt_sec_debug_en(g));
nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x",
g->ops.fuse.fuse_opt_priv_sec_en(g));
nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val);
nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
if (g->ops.fuse.read_gcplex_config_fuse(g, &val) != 0) {
nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
}
}
bool gm20b_pmu_is_debug_mode_en(struct gk20a *g)