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gpu: nvgpu: add NVGPU_SUPPORT_PLC flag

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Add NVGPU_SUPPORT_PLC to indicate if compression PLC is supported in
nvgpu.
Add corresponding GPU characteristics flag and IOCTL mapping to sync
compression support status with nvrm_gpu.

JIRA NVGPU-4666

Change-Id: I63307b99ceac7dc2e6af143ca13cdac63e253ed3
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340242
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2020-05-05 12:51:31 -07:00
committed by Alex Waterman
parent 2a3bb9107f
commit 32bdf8cc2d
3 changed files with 9 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/include/nvgpu/enabled.h
View File

@@ -258,10 +258,13 @@ struct gk20a;
/** SM TTU is enabled */
#define NVGPU_SUPPORT_SM_TTU 88U
/** PLC Compression */
#define NVGPU_SUPPORT_PLC 89U
/*
* Must be greater than the largest bit offset in the above list.
*/
#define NVGPU_MAX_ENABLED_BITS 89U
#define NVGPU_MAX_ENABLED_BITS 90U
/**
* @brief Check if the passed flag is enabled.

4
drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
View File

@@ -254,7 +254,9 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
{NVGPU_GPU_FLAGS_SUPPORT_COMPRESSION,
NVGPU_SUPPORT_COMPRESSION},
{NVGPU_GPU_FLAGS_SUPPORT_SM_TTU,
NVGPU_SUPPORT_SM_TTU}
NVGPU_SUPPORT_SM_TTU},
{NVGPU_GPU_FLAGS_SUPPORT_PLC,
NVGPU_SUPPORT_PLC}
};
static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)

2
include/uapi/linux/nvgpu.h
View File

@@ -177,6 +177,8 @@ struct nvgpu_gpu_zbc_query_table_args {
#define NVGPU_GPU_FLAGS_SUPPORT_COMPRESSION (1ULL << 36)
/* SM TTU is enabled */
#define NVGPU_GPU_FLAGS_SUPPORT_SM_TTU (1ULL << 37)
/* Compression PLC is enabled */
#define NVGPU_GPU_FLAGS_SUPPORT_PLC (1ULL << 38)
/* SM LRF ECC is enabled */
#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
/* SM SHM ECC is enabled */