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gpu: nvgpu: export gv11b fifo APIs

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Export below APIs from fifo_gv11b.h
gv11b_fifo_init_ramfc_eng_method_buffer()
gv11b_userd_writeback_config()

Also move #define PBDMA_SUBDEVICE_ID to header file

Jira NVGPUT-19

Change-Id: I5e3abf02acfe014e39550f236d60d8991a75b4ef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699315
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-04-20 00:55:00 -07:00
committed by mobile promotions
parent ae04f394cf
commit 32f6ffee13
2 changed files with 8 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -58,11 +58,6 @@
#include "gr_gv11b.h" #include "gr_gv11b.h"
#include "mc_gv11b.h" #include "mc_gv11b.h"
#define PBDMA_SUBDEVICE_ID 1
static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g,
struct channel_gk20a *ch, struct nvgpu_mem *mem);
void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist)
{ {
@@ -128,7 +123,7 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
runlist[0], runlist[1], runlist[2], runlist[3]); runlist[0], runlist[1], runlist[2], runlist[3]);
} }
static void gv11b_userd_writeback_config(struct gk20a *g) void gv11b_userd_writeback_config(struct gk20a *g)
{ {
gk20a_writel(g, fifo_userd_writeback_r(), fifo_userd_writeback_timer_f( gk20a_writel(g, fifo_userd_writeback_r(), fifo_userd_writeback_timer_f(
fifo_userd_writeback_timer_100us_v())); fifo_userd_writeback_timer_100us_v()));
@@ -1567,7 +1562,7 @@ unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g,
return rc_type; return rc_type;
} }
static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g,
struct channel_gk20a *ch, struct nvgpu_mem *mem) struct channel_gk20a *ch, struct nvgpu_mem *mem)
{ {
struct tsg_gk20a *tsg; struct tsg_gk20a *tsg;

6
drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
View File

@@ -25,6 +25,8 @@
#ifndef FIFO_GV11B_H #ifndef FIFO_GV11B_H
#define FIFO_GV11B_H #define FIFO_GV11B_H
#define PBDMA_SUBDEVICE_ID 1
#define FIFO_INVAL_PBDMA_ID ((u32)~0) #define FIFO_INVAL_PBDMA_ID ((u32)~0)
#define FIFO_INVAL_VEID ((u32)~0) #define FIFO_INVAL_VEID ((u32)~0)
@@ -117,4 +119,8 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g);
void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch);
u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g); u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g);
void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g,
struct channel_gk20a *ch, struct nvgpu_mem *mem);
void gv11b_userd_writeback_config(struct gk20a *g);
#endif #endif