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gpu: nvgpu: add HAL to set ppriv timeouts

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Add new HAL gops.bus.set_ppriv_timeout_settings() to set platform specific
ppriv timeouts
Set this HAL for all supported GPUs for now

Jira NVGPUT-35

Change-Id: I88b438a7bf381d0216e0947a16cd267461d0e8d7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699314
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-04-19 07:14:28 -07:00
committed by mobile promotions
parent f85f21d1a5
commit ae04f394cf
11 changed files with 32 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/gk20a/bus_gk20a.c
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@@ -34,6 +34,9 @@
#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
void gk20a_bus_init_hw(struct gk20a *g)
{
@@ -172,3 +175,14 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
return 0;
}
void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g)
{
/*
* Bug 1340570: increase the clock timeout to avoid potential
* operation failure at high gpcclk rate. Default values are 0x400.
*/
nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
}

1
drivers/gpu/nvgpu/gk20a/bus_gk20a.h
View File

@@ -32,5 +32,6 @@ void gk20a_bus_isr(struct gk20a *g);
int gk20a_read_ptimer(struct gk20a *g, u64 *value);
void gk20a_bus_init_hw(struct gk20a *g);
int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst);
void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g);
#endif /* GK20A_H */

1
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -1094,6 +1094,7 @@ struct gpu_ops {
u32 source_id, u32 count,
struct nvgpu_cpu_time_correlation_sample *);
int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
void (*set_ppriv_timeout_settings)(struct gk20a *g);
} bus;
struct {

11
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -53,9 +53,6 @@
#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
#include <nvgpu/hw/gk20a/hw_top_gk20a.h>
#include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
#include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
@@ -4489,12 +4486,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
gr_gk20a_zcull_init_hw(g, gr);
/* Bug 1340570: increase the clock timeout to avoid potential
* operation failure at high gpcclk rate. Default values are 0x400.
*/
gk20a_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
gk20a_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
gk20a_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
if (g->ops.bus.set_ppriv_timeout_settings)
g->ops.bus.set_ppriv_timeout_settings(g);
/* enable fifo access */
gk20a_writel(g, gr_gpfifo_ctl_r(),

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -597,6 +597,8 @@ static const struct gpu_ops gm20b_ops = {
.read_ptimer = gk20a_read_ptimer,
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
.bar1_bind = gm20b_bus_bar1_bind,
.set_ppriv_timeout_settings =
gk20a_bus_set_ppriv_timeout_settings,
},
#if defined(CONFIG_GK20A_CYCLE_STATS)
.css = {

2
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -711,6 +711,8 @@ static const struct gpu_ops gp106_ops = {
.read_ptimer = gk20a_read_ptimer,
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
.bar1_bind = gk20a_bus_bar1_bind,
.set_ppriv_timeout_settings =
gk20a_bus_set_ppriv_timeout_settings,
},
#if defined(CONFIG_GK20A_CYCLE_STATS)
.css = {

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -644,6 +644,8 @@ static const struct gpu_ops gp10b_ops = {
.read_ptimer = gk20a_read_ptimer,
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
.bar1_bind = gk20a_bus_bar1_bind,
.set_ppriv_timeout_settings =
gk20a_bus_set_ppriv_timeout_settings,
},
#if defined(CONFIG_GK20A_CYCLE_STATS)
.css = {

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -771,6 +771,8 @@ static const struct gpu_ops gv100_ops = {
.read_ptimer = gk20a_read_ptimer,
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
.bar1_bind = NULL,
.set_ppriv_timeout_settings =
gk20a_bus_set_ppriv_timeout_settings,
},
#if defined(CONFIG_GK20A_CYCLE_STATS)
.css = {

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -709,6 +709,8 @@ static const struct gpu_ops gv11b_ops = {
.read_ptimer = gk20a_read_ptimer,
.get_timestamps_zipper = nvgpu_get_timestamps_zipper,
.bar1_bind = NULL,
.set_ppriv_timeout_settings =
gk20a_bus_set_ppriv_timeout_settings,
},
#if defined(CONFIG_GK20A_CYCLE_STATS)
.css = {

2
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -519,6 +519,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.read_ptimer = vgpu_read_ptimer,
.get_timestamps_zipper = vgpu_get_timestamps_zipper,
.bar1_bind = gk20a_bus_bar1_bind,
.set_ppriv_timeout_settings =
gk20a_bus_set_ppriv_timeout_settings,
},
#if defined(CONFIG_GK20A_CYCLE_STATS)
.css = {

2
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -566,6 +566,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.read_ptimer = vgpu_read_ptimer,
.get_timestamps_zipper = vgpu_get_timestamps_zipper,
.bar1_bind = NULL,
.set_ppriv_timeout_settings =
gk20a_bus_set_ppriv_timeout_settings,
},
#if defined(CONFIG_GK20A_CYCLE_STATS)
.css = {