nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 09:57:08 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Modify dgpu WPR/NON-WPR address space

Browse Source 
Currently, there is free space of 3MB with current implementation due to
gap between WPR & NON-WPR offset, with this PMU buffers are allocated
between this space & some are after WPR.

So, modified WPR to allocate at 0th offset of bootstrap-region of VIDMEM
& NON-WPR to be at WPR+WPR_SIZE offset of bootstrap-region to make
contiguous free space available till end of bootstrap-region of VIDMEM.

Increased WPR/NON-WPR size from 1MB to 2MB as LS falcon managed
count increased to 4 for Turing & remains 2MB for previous chips too.

Bug 200476497

Change-Id: I92ca5bc9a571330d75a66ce820a1c82442c1f200
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994653
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-01-14 16:07:38 +05:30
committed by mobile promotions
parent dd4c60aeb5
commit 33e9d08610
1 changed files with 3 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/common/pmu/acr_gp106.c
View File

@@ -54,10 +54,7 @@ typedef int (*gp106_get_ucode_details)(struct gk20a *g,
struct flcn_ucode_img_v1 *udata);
/* Both size and address of WPR need to be 128K-aligned */
#define WPR_ALIGNMENT 0x20000U
#define GP106_DGPU_NONWPR NVGPU_VIDMEM_BOOTSTRAP_ALLOCATOR_BASE
#define GP106_DGPU_WPR_OFFSET 0x400000U
#define DGPU_WPR_SIZE 0x100000U
#define DGPU_WPR_SIZE 0x200000U
/*Externs*/
@@ -73,8 +70,8 @@ static gp106_get_ucode_details pmu_acr_supp_ucode_list[] = {
void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
{
inf->nonwpr_base = g->mm.vidmem.bootstrap_base;
inf->wpr_base = inf->nonwpr_base + GP106_DGPU_WPR_OFFSET;
inf->wpr_base = g->mm.vidmem.bootstrap_base;
inf->nonwpr_base = inf->wpr_base + DGPU_WPR_SIZE;
inf->size = DGPU_WPR_SIZE;
}