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gpu: nvgpu: remove unnecessary asserts in common.gr hal subunits

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Below functions in common.gr hal subunits include unnecessary
asserts to ensure value is not truncated when parsing into U32 size.

gm20b_gr_init_commit_global_attrib_cb()
gp10b_gr_init_commit_global_bundle_cb()
gp10b_gr_init_commit_global_pagepool()
gv11b_gr_init_commit_global_attrib_cb()

Make use of nvgpu_safe_cast_u64_to_u32() and remove unnecessary
asserts

gp10b_gr_init_commit_global_bundle_cb() function checks if size <=
U32_MAX value. But since size is declared as u32, it will always be
<= U32_MAX value so there is no point in the check.
Remove unnecessary check.

Jira NVGPU-4778

Change-Id: I9562afd1b31c3c6b095f607cbdf725d33d87effb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279898
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Deepak Nibade
2020-01-13 13:57:41 +05:30
committed by Alex Waterman
parent b85c8b2b7c
commit 340f35d76e
3 changed files with 4 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b_fusa.c
View File

@@ -420,9 +420,8 @@ void gm20b_gr_init_commit_global_attrib_cb(struct gk20a *g,
addr = addr >> gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v();
nvgpu_log_info(g, "attrib cb addr : 0x%016llx", addr);
nvgpu_assert(u64_hi32(addr) == 0U);
cb_addr = (u32)addr;
cb_addr = nvgpu_safe_cast_u64_to_u32(addr);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_setup_attrib_cb_base_r(),
gr_gpcs_setup_attrib_cb_base_addr_39_12_f(cb_addr) |
gr_gpcs_setup_attrib_cb_base_valid_true_f(), patch);

9
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b_fusa.c
View File

@@ -121,14 +121,10 @@ void gp10b_gr_init_commit_global_bundle_cb(struct gk20a *g,
nvgpu_log_info(g, "bundle cb addr : 0x%016llx, size : %u",
addr, size);
nvgpu_assert(u64_hi32(addr) == 0U);
cb_addr = (u32)addr;
cb_addr = nvgpu_safe_cast_u64_to_u32(addr);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_bundle_cb_base_r(),
gr_scc_bundle_cb_base_addr_39_8_f(cb_addr), patch);
NVGPU_COV_WHITELIST(false_positive, NVGPU_MISRA(Rule, 14_3), "Bug 2615925")
nvgpu_assert(size <= U32_MAX);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_bundle_cb_size_r(),
gr_scc_bundle_cb_size_div_256b_f(size) |
gr_scc_bundle_cb_size_valid_true_f(), patch);
@@ -178,11 +174,10 @@ void gp10b_gr_init_commit_global_pagepool(struct gk20a *g,
size = gr_scc_pagepool_total_pages_hwmax_v();
}
nvgpu_assert(u64_hi32(addr) == 0U);
nvgpu_log_info(g, "pagepool buffer addr : 0x%016llx, size : %lu",
addr, size);
pp_addr = (u32)addr;
pp_addr = nvgpu_safe_cast_u64_to_u32(addr);
pp_size = nvgpu_safe_cast_u64_to_u32(size);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_scc_pagepool_base_r(),
gr_scc_pagepool_base_addr_39_8_f(pp_addr), patch);

4
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b_fusa.c
View File

@@ -715,9 +715,7 @@ void gv11b_gr_init_commit_global_attrib_cb(struct gk20a *g,
attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f();
nvgpu_assert(u64_hi32(addr) == 0U);
cb_addr = (u32)addr;
cb_addr = nvgpu_safe_cast_u64_to_u32(addr);
nvgpu_gr_ctx_patch_write(g, gr_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(),
gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(cb_addr) |
gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch);