gpu: nvgpu: remove gr_gk20a.h from gk20a.h

Remove gr_gk20a.h from gk20a.h
Add gr_gk20a.h in all gr hal files

Removed ununsed gr_priv.h from two files

Jira NVGPU-3217
Jira NVGPU-3218

Change-Id: Ic74c068782432e99ddba168f65a5cf42e1405305
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104569
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr_falcon.c

@@ -35,7 +35,6 @@
 #include <nvgpu/dma.h>
 
 #include "gr_falcon_priv.h"
-#include "common/gr/gr_priv.h"
 
 #define NVGPU_FECS_UCODE_IMAGE	"fecs.bin"
 #define NVGPU_GPCCS_UCODE_IMAGE	"gpccs.bin"
@@ -477,7 +476,6 @@ int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g,
 					struct nvgpu_gr_falcon *falcon)
 {
 	int err;
-	struct nvgpu_gr *gr = g->gr;
 
 	nvgpu_log_fn(g, " ");
 
@@ -494,14 +492,14 @@ int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g,
 		nvgpu_gr_falcon_load_imem(g);
 		g->ops.gr.falcon.start_ucode(g);
 	} else {
-		if (!gr->falcon->skip_ucode_init) {
+		if (!falcon->skip_ucode_init) {
 			err =  nvgpu_gr_falcon_init_ctxsw_ucode(g, falcon);
 			if (err != 0) {
 				return err;
 			}
 		}
 		nvgpu_gr_falcon_load_with_bootloader(g, falcon);
-		gr->falcon->skip_ucode_init = true;
+		falcon->skip_ucode_init = true;
 	}
 	nvgpu_log_fn(g, "done");
 	return 0;

drivers/gpu/nvgpu/common/rc/rc.c

@@ -32,7 +32,6 @@
 #include <nvgpu/pbdma_status.h>
 #include <nvgpu/debug.h>
 #include <nvgpu/rc.h>
-#include "common/gr/gr_priv.h"
 
 void nvgpu_rc_fifo_recover(struct gk20a *g, u32 eng_bitmask,
 			u32 hw_id, bool id_is_tsg,

drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -83,6 +83,8 @@
 #include "common/vgpu/init/init_vgpu.h"
 #include "vgpu_hal_gp10b.h"
 
+#include "gk20a/gr_gk20a.h"
+
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/gr_gp10b.h"
 

drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -93,6 +93,8 @@
 #include "common/vgpu/ptimer/ptimer_vgpu.h"
 #include "vgpu_hal_gv11b.h"
 
+#include "gk20a/gr_gk20a.h"
+
 #include <gm20b/gr_gm20b.h>
 #include <gm20b/mm_gm20b.h>
 

drivers/gpu/nvgpu/gk20a/gr_gk20a.h

@@ -31,13 +31,6 @@
 struct nvgpu_gr_ctx;
 struct channel_gk20a;
 struct nvgpu_warpstate;
-struct nvgpu_gr_ctx_desc;
-struct nvgpu_gr_falcon;
-struct nvgpu_gr_global_ctx_buffer_desc;
-struct nvgpu_gr_zbc;
-struct nvgpu_gr_hwpm_map;
-struct nvgpu_gr_isr_data;
-struct nvgpu_gr_ctx_desc;
 struct dbg_session_gk20a;
 struct nvgpu_dbg_reg_op;
 

drivers/gpu/nvgpu/gv11b/gr_gv11b.c

@@ -50,6 +50,8 @@
 #include "gk20a/gr_pri_gk20a.h"
 #include "common/gr/gr_priv.h"
 
+#include "gk20a/gr_gk20a.h"
+
 #include "gm20b/gr_gm20b.h"
 
 #include "gp10b/gr_gp10b.h"

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -96,6 +96,7 @@
 #include "common/fifo/channel_gm20b.h"
 #include "common/pmu/pg/pg_sw_gm20b.h"
 
+#include "gk20a/gr_gk20a.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/mm_gm20b.h"
 #include "hal_gm20b.h"

drivers/gpu/nvgpu/hal/init/hal_gp10b.c

@@ -116,6 +116,7 @@
 #include "common/fifo/channel_gm20b.h"
 #include "common/clk_arb/clk_arb_gp10b.h"
 
+#include "gk20a/gr_gk20a.h"
 
 #include "gp10b/gr_gp10b.h"
 #include "gp10b/mm_gp10b.h"

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -135,6 +135,7 @@
 #include "common/fifo/channel_gv11b.h"
 #include "common/fifo/channel_gv100.h"
 
+#include "gk20a/gr_gk20a.h"
 
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/mm_gm20b.h"

drivers/gpu/nvgpu/hal/init/hal_gv11b.c

@@ -129,6 +129,7 @@
 #include "common/fifo/channel_gv11b.h"
 #include "common/clk_arb/clk_arb_gp10b.h"
 
+#include "gk20a/gr_gk20a.h"
 
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/mm_gm20b.h"

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -148,6 +148,7 @@
 #include "hal/fifo/pbdma_status_gm20b.h"
 #include "common/clk_arb/clk_arb_gv100.h"
 
+#include "gk20a/gr_gk20a.h"
 
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/mm_gm20b.h"

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -74,7 +74,6 @@ struct nvgpu_engine_status_info;
 struct nvgpu_pbdma_status_info;
 struct nvgpu_gr_config;
 struct nvgpu_fecs_method_op;
-enum nvgpu_nvlink_minion_dlcmd;
 struct nvgpu_cbc;
 struct nvgpu_mem;
 struct gk20a_cs_snapshot_client;
@@ -87,6 +86,15 @@ struct nvgpu_preemption_modes_rec;
 struct nvgpu_gr_ctx;
 struct nvgpu_fecs_host_intr_status;
 struct nvgpu_fecs_ecc_status;
+struct _resmgr_context;
+struct nvgpu_gpfifo_entry;
+
+enum nvgpu_unit;
+enum nvgpu_flush_op;
+enum gk20a_mem_rw_flag;
+enum nvgpu_nvlink_minion_dlcmd;
+enum ctxsw_addr_type;
+
 typedef void (*global_ctx_mem_destroy_fn)(struct gk20a *g,
 					struct nvgpu_mem *mem);
 
@@ -113,7 +121,6 @@ typedef void (*global_ctx_mem_destroy_fn)(struct gk20a *g,
 
 #include "hal/clk/clk_gk20a.h"
 #include "gk20a/fifo_gk20a.h"
-#include "gk20a/gr_gk20a.h"
 
 #ifdef CONFIG_DEBUG_FS
 struct railgate_stats {
@@ -180,14 +187,6 @@ struct railgate_stats {
 
 #define MAX_TPC_PG_CONFIGS      3
 
-enum nvgpu_unit;
-
-enum nvgpu_flush_op;
-enum gk20a_mem_rw_flag;
-
-struct _resmgr_context;
-struct nvgpu_gpfifo_entry;
-
 struct nvgpu_gpfifo_userdata {
 	struct nvgpu_gpfifo_entry __user *entries;
 	struct _resmgr_context *context;

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -40,6 +40,7 @@
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/fence.h>
 
+#include "gk20a/gr_gk20a.h"
 #include "common/gr/gr_priv.h"
 
 #include "ioctl_ctrl.h"