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gpu: nvgpu: clean ramfc dependencies

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Remove ramfc dependencies on fifo hw header.

Added the following HALs:
- fifo.get_runlist_timeslice
- fifo.get_pb_timeslice

Jira NVGPU-3199

Change-Id: I1bdd4ee5e4008676df514b9d8563e862d1d68e33
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104539
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-04-24 14:45:00 -07:00
committed by mobile promotions
parent ef524ee0d1
commit 157b43ed16
10 changed files with 29 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
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@@ -142,3 +142,16 @@ int gk20a_fifo_init_pbdma_map(struct gk20a *g, u32 *pbdma_map, u32 num_pbdma)
return 0;
}
u32 gk20a_fifo_get_runlist_timeslice(struct gk20a *g)
{
return fifo_runlist_timeslice_timeout_128_f() |
fifo_runlist_timeslice_timescale_3_f() |
fifo_runlist_timeslice_enable_true_f();
}
u32 gk20a_fifo_get_pb_timeslice(struct gk20a *g) {
return fifo_pb_timeslice_timeout_16_f() |
fifo_pb_timeslice_timescale_0_f() |
fifo_pb_timeslice_enable_true_f();
}

2
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
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@@ -245,5 +245,7 @@ static inline void gk20a_fifo_profile_snapshot(
u32 gk20a_fifo_default_timeslice_us(struct gk20a *g);
int gk20a_fifo_init_pbdma_map(struct gk20a *g, u32 *pbdma_map, u32 num_pbdma);
u32 gk20a_fifo_get_runlist_timeslice(struct gk20a *g);
u32 gk20a_fifo_get_pb_timeslice(struct gk20a *g);
#endif /* FIFO_GK20A_H */

9
drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c
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@@ -29,7 +29,6 @@
#include "ramfc_gk20a.h"
#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
int gk20a_ramfc_commit_userd(struct channel_gk20a *ch)
@@ -93,14 +92,10 @@ int gk20a_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
g->ops.pbdma.acquire_val(pbdma_acquire_timeout));
nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(),
fifo_runlist_timeslice_timeout_128_f() |
fifo_runlist_timeslice_timescale_3_f() |
fifo_runlist_timeslice_enable_true_f());
g->ops.fifo.get_runlist_timeslice(g));
nvgpu_mem_wr32(g, mem, ram_fc_pb_timeslice_w(),
fifo_pb_timeslice_timeout_16_f() |
fifo_pb_timeslice_timescale_0_f() |
fifo_pb_timeslice_enable_true_f());
g->ops.fifo.get_pb_timeslice(g));
nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(ch->chid));

1
drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c
View File

@@ -31,7 +31,6 @@
#include "hal/fifo/ramfc_gk20a.h"
#include "hal/fifo/ramfc_tu104.h"
#include <nvgpu/hw/tu104/hw_pbdma_tu104.h>
#include <nvgpu/hw/tu104/hw_ram_tu104.h>
int tu104_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -693,6 +693,8 @@ static const struct gpu_ops gm20b_ops = {
.get_mmu_fault_client_desc =
gk20a_fifo_get_mmu_fault_client_desc,
.get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc,
.get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice,
.get_pb_timeslice = gk20a_fifo_get_pb_timeslice,
.is_mmu_fault_pending = gk20a_fifo_is_mmu_fault_pending,
},
.engine = {

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -760,6 +760,8 @@ static const struct gpu_ops gp10b_ops = {
.get_mmu_fault_client_desc =
gp10b_fifo_get_mmu_fault_client_desc,
.get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc,
.get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice,
.get_pb_timeslice = gk20a_fifo_get_pb_timeslice,
.is_mmu_fault_pending = gk20a_fifo_is_mmu_fault_pending,
},
.engine = {

2
drivers/gpu/nvgpu/hal/init/hal_gv100.c
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@@ -940,6 +940,8 @@ static const struct gpu_ops gv100_ops = {
.get_mmu_fault_desc = NULL,
.get_mmu_fault_client_desc = NULL,
.get_mmu_fault_gpc_desc = NULL,
.get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice,
.get_pb_timeslice = gk20a_fifo_get_pb_timeslice,
.mmu_fault_id_to_pbdma_id = gv11b_fifo_mmu_fault_id_to_pbdma_id,
},
.engine = {

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -913,6 +913,8 @@ static const struct gpu_ops gv11b_ops = {
.get_mmu_fault_desc = NULL,
.get_mmu_fault_client_desc = NULL,
.get_mmu_fault_gpc_desc = NULL,
.get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice,
.get_pb_timeslice = gk20a_fifo_get_pb_timeslice,
.mmu_fault_id_to_pbdma_id = gv11b_fifo_mmu_fault_id_to_pbdma_id,
},
.engine = {

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -975,6 +975,8 @@ static const struct gpu_ops tu104_ops = {
.get_mmu_fault_desc = NULL,
.get_mmu_fault_client_desc = NULL,
.get_mmu_fault_gpc_desc = NULL,
.get_runlist_timeslice = gk20a_fifo_get_runlist_timeslice,
.get_pb_timeslice = gk20a_fifo_get_pb_timeslice,
.mmu_fault_id_to_pbdma_id = gv11b_fifo_mmu_fault_id_to_pbdma_id,
},
.engine = {

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -1035,6 +1035,8 @@ struct gpu_ops {
void (*get_mmu_fault_client_desc)(
struct mmu_fault_info *mmfault);
void (*get_mmu_fault_gpc_desc)(struct mmu_fault_info *mmfault);
u32 (*get_runlist_timeslice)(struct gk20a *g);
u32 (*get_pb_timeslice)(struct gk20a *g);
bool (*is_mmu_fault_pending)(struct gk20a *g);
u32 (*mmu_fault_id_to_pbdma_id)(struct gk20a *g,
u32 mmu_fault_id);