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gpu: nvgpu: fix CERT-C issues in ltc intr driver

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Use nvgpu_safe_add_u32 for u32 additions in ltc interrupt
driver.

JIRA NVGPU-3623

Change-Id: If4d1b126836c5980e7016ed42b588b435f4f7f66
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135322
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2019-06-12 13:27:48 -07:00
committed by mobile promotions
parent 466592e639
commit 344eceb739
2 changed files with 10 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gp10b.c
View File

@@ -79,8 +79,8 @@ void gp10b_ltc_intr_handle_lts_interrupts(struct gk20a *g, u32 ltc, u32 slice)
"Double bit error detected in GPU L2!"); "Double bit error detected in GPU L2!");
ecc_stats_reg_val = ecc_stats_reg_val =
nvgpu_readl(g, nvgpu_readl(g, nvgpu_safe_add_u32(
ltc_ltc0_lts0_dstg_ecc_report_r() + offset); ltc_ltc0_lts0_dstg_ecc_report_r(), offset));
g->ecc.ltc.ecc_ded_count[ltc][slice].counter = g->ecc.ltc.ecc_ded_count[ltc][slice].counter =
nvgpu_safe_add_u32( nvgpu_safe_add_u32(
g->ecc.ltc.ecc_ded_count[ltc][slice].counter, g->ecc.ltc.ecc_ded_count[ltc][slice].counter,

11
drivers/gpu/nvgpu/hal/ltc/intr/ltc_intr_gv11b.c
View File

@@ -154,9 +154,14 @@ static void gv11b_ltc_intr_handle_lts_interrupts(struct gk20a *g,
ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()); ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s());
} }
g->ecc.ltc.ecc_sec_count[ltc][slice].counter += corrected_delta; g->ecc.ltc.ecc_sec_count[ltc][slice].counter =
g->ecc.ltc.ecc_ded_count[ltc][slice].counter += nvgpu_safe_add_u32(
uncorrected_delta; g->ecc.ltc.ecc_sec_count[ltc][slice].counter,
corrected_delta);
g->ecc.ltc.ecc_ded_count[ltc][slice].counter =
nvgpu_safe_add_u32(
g->ecc.ltc.ecc_ded_count[ltc][slice].counter,
uncorrected_delta);
nvgpu_log(g, gpu_dbg_intr, nvgpu_log(g, gpu_dbg_intr,
"ltc:%d lts: %d cache ecc interrupt intr: 0x%x", "ltc:%d lts: %d cache ecc interrupt intr: 0x%x",
ltc, slice, ltc_intr3); ltc, slice, ltc_intr3);