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gpu: nvgpu: fix Misc MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Icb724f3424c8161c12b69d373ff08c7648f79e56 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1834225 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -273,7 +273,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
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pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
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&ack_status, 1);
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if (ack_status == 0) {
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if (ack_status == 0U) {
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status = -EINVAL;
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nvgpu_err(g, "MCLK-CHANGE ACK failed");
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}
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@@ -306,7 +306,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
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pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
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&ack_status, 1);
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if (ack_status == 0) {
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if (ack_status == 0U) {
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status = -EINVAL;
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nvgpu_err(g, "post-init ack failed");
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}
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