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gpu: nvgpu: fix Misc MISRA Rule 10.4 Violations

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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: Icb724f3424c8161c12b69d373ff08c7648f79e56
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1834225
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sai Nikhil
2018-12-06 15:07:47 +05:30
committed by mobile promotions
parent 8d2c1141d3
commit 34ef8ee49f
13 changed files with 67 additions and 67 deletions
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6
drivers/gpu/nvgpu/pstate/pstate.c
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@@ -267,7 +267,7 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
if (g->ops.clk.support_clk_freq_domain) {
err = nvgpu_clk_freq_domain_pmu_setup(g);
if (err != 0) {
if (err != 0U) {
return err;
}
}
@@ -393,7 +393,7 @@ static int parse_pstate_entry_5x(struct gk20a *g,
(void) memset(pstate, 0, sizeof(struct pstate));
pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X;
pstate->num = 0x0F - entry->pstate_level;
pstate->num = 0x0FU - U32(entry->pstate_level);
pstate->clklist.num_info = hdr->clock_entry_count;
pstate->lpwr_entry_idx = entry->lpwr_entry_idx;
@@ -443,7 +443,7 @@ static int parse_pstate_table_5x(struct gk20a *g,
int err = 0;
if ((hdr->header_size != VBIOS_PSTATE_HEADER_5X_SIZE_10) ||
(hdr->base_entry_count == 0) ||
(hdr->base_entry_count == 0U) ||
((hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2) &&
(hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3) &&
(hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_6X_SIZE_5)) ||