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gpu: nvgpu: update hw header with hwcfg1 register and imem, dmem ports values

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To validate the imem & dmem port being accessed by nvgpu, allowed ports
need to be known from hwcfg1 register. Update the hw header with these
to use for checking the valid ports in later patch.

JIRA NVGPU-1993

Change-Id: I1146a85d452d02fefcc75065a0cd546fff688fd2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030622
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-02-28 15:11:31 +05:30
committed by mobile promotions
parent 0ef974e020
commit 35ec51cb2e
1 changed files with 13 additions and 1 deletions
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14
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_falcon_gm20b.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -414,6 +414,18 @@ static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
{
return (r >> 9U) & 0x1ffU;
}
static inline u32 falcon_falcon_hwcfg1_r(void)
{
return 0x0000012cU;
}
static inline u32 falcon_falcon_hwcfg1_imem_ports_v(u32 r)
{
return (r >> 8U) & 0xfU;
}
static inline u32 falcon_falcon_hwcfg1_dmem_ports_v(u32 r)
{
return (r >> 12U) & 0xfU;
}
static inline u32 falcon_falcon_dmatrfbase_r(void)
{
return 0x00000110U;