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35ec51cb2e
To validate the imem & dmem port being accessed by nvgpu, allowed ports need to be known from hwcfg1 register. Update the hw header with these to use for checking the valid ports in later patch. JIRA NVGPU-1993 Change-Id: I1146a85d452d02fefcc75065a0cd546fff688fd2 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2030622 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>