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gpu: nvgpu: tu104: do not map PCE0 to any LCE

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Configure PCE/LCE mapping as follows:
- PCE0 (HSHUB) is unconnected
- GR_CE1, LCE4 share PCE1 (HSHUB)
- LCE2 gets PCE2 (FBHUB)
- GR_CE0, LCE3 share PCE3 (FBHUB)

Bug 2494068

Change-Id: I25ddf7976f67f3faf3a9ef8cf79dcd9619ab5e63
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151041
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-07-10 10:10:29 -04:00
committed by mobile promotions
parent 63f1861f4c
commit 3659c2f0c1
8 changed files with 102 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/nvgpu-hal-new.yaml
View File

@@ -371,7 +371,9 @@ ce:
hal/ce/ce_gp10b_fusa.c,
hal/ce/ce_gp10b.h,
hal/ce/ce_gv11b_fusa.c,
hal/ce/ce_gv11b.h ]
hal/ce/ce_gv11b.h,
hal/ce/ce_tu104.c,
hal/ce/ce_tu104.h ]
gr:
safe: yes

1
drivers/gpu/nvgpu/Makefile
View File

@@ -673,6 +673,7 @@ nvgpu-y += \
hal/top/top_gv11b_fusa.o
nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
hal/ce/ce_tu104.o \
hal/init/hal_gp10b.o \
hal/init/hal_gp10b_litter.o \
hal/init/hal_gm20b.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -316,7 +316,6 @@ srcs += hal/init/hal_gp10b.c \
hal/pmu/pmu_gp106.c \
hal/top/top_gm20b.c \
hal/top/top_gp106.c
endif
ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
@@ -576,6 +575,7 @@ srcs += common/sec2/sec2.c \
hal/mc/mc_tu104.c \
hal/bus/bus_gv100.c \
hal/bus/bus_tu104.c \
hal/ce/ce_tu104.c \
hal/class/class_tu104.c \
hal/clk/clk_gv100.c \
hal/gr/ecc/ecc_tu104.c \

4
drivers/gpu/nvgpu/common/ce/ce.c
View File

@@ -409,6 +409,10 @@ int nvgpu_ce_init_support(struct gk20a *g)
struct nvgpu_ce_app *ce_app = g->ce_app;
u32 ce_reset_mask;
if (g->ops.ce.set_pce2lce_mapping != NULL) {
g->ops.ce.set_pce2lce_mapping(g);
}
if (unlikely(ce_app == NULL)) {
ce_app = nvgpu_kzalloc(g, sizeof(*ce_app));
if (ce_app == NULL) {

61
drivers/gpu/nvgpu/hal/ce/ce_tu104.c Normal file
View File

@@ -0,0 +1,61 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/log.h>
#include <nvgpu/io.h>
#include "ce_tu104.h"
#include <nvgpu/hw/tu104/hw_ce_tu104.h>
void tu104_ce_set_pce2lce_mapping(struct gk20a *g)
{
/*
* By default GRCE0 and GRCE1 share PCE0.
* Do not change PCE0 config until GRCEs are remapped to PCE1/PCE3.
*/
/* PCE1 (HSHUB) is assigned to LCE4 */
nvgpu_writel(g, ce_pce2lce_config_r(1),
ce_pce2lce_config_pce_assigned_lce_f(4));
/* GRCE1 shares with LCE4 */
nvgpu_writel(g, ce_grce_config_r(1),
ce_grce_config_shared_lce_f(4) |
ce_grce_config_shared_f(1));
/* PCE2 (FBHUB) is assigned to LCE2 */
nvgpu_writel(g, ce_pce2lce_config_r(2),
ce_pce2lce_config_pce_assigned_lce_f(2));
/* PCE3 (FBHUB) is assigned to LCE3 */
nvgpu_writel(g, ce_pce2lce_config_r(3),
ce_pce2lce_config_pce_assigned_lce_f(3));
/* GRCE0 shares with LCE3 */
nvgpu_writel(g, ce_grce_config_r(0),
ce_grce_config_shared_lce_f(3) |
ce_grce_config_shared_f(1));
/* PCE0 (HSHUB) is unconnected */
nvgpu_writel(g, ce_pce2lce_config_r(0),
ce_pce2lce_config_pce_assigned_lce_none_f());
}

29
drivers/gpu/nvgpu/hal/ce/ce_tu104.h Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_CE_TU104_H
#define NVGPU_CE_TU104_H
struct gk20a;
void tu104_ce_set_pce2lce_mapping(struct gk20a *g);
#endif /* NVGPU_CE_TU104_H */

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -42,6 +42,7 @@
#include "hal/bus/bus_tu104.h"
#include "hal/ce/ce_gp10b.h"
#include "hal/ce/ce_gv11b.h"
#include "hal/ce/ce_tu104.h"
#include "hal/class/class_tu104.h"
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/priv_ring/priv_ring_gp10b.h"
@@ -260,6 +261,7 @@ static const struct gpu_ops tu104_ops = {
},
#endif
.ce = {
.set_pce2lce_mapping = tu104_ce_set_pce2lce_mapping,
.isr_stall = gv11b_ce_stall_isr,
.isr_nonstall = NULL,
.get_num_pce = gv11b_ce_get_num_pce,

1
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -281,6 +281,7 @@ struct gpu_ops {
} cbc;
#endif
struct {
void (*set_pce2lce_mapping)(struct gk20a *g);
void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);
u32 (*isr_nonstall)(struct gk20a *g, u32 inst_id, u32 pri_base);
u32 (*get_num_pce)(struct gk20a *g);