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gpu: nvgpu: skip channel abort for deferred reset

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In case deferred_reset_pending is set in gk20a_fifo_handle_mmu_fault() and in
gv11b_fifo_teardown_ch_tsg(), we skip resetting the engines and skip setting
the error notifier
Then we call gk20a_channel_abort()/gk20a_fifo_abort_tsg() which aborts the
channels, and resets the syncpoint values to release all the waiters

But since we don't set error notifier this could lead User to assume a
successful submission without any error

To fix this disable channel/TSG in case deferred_reset_pending is set and skip
calls to gk20a_channel_abort()/gk20a_fifo_abort_tsg()

Note that we finally abort the channel when channel is being closed

Bug 200363077

Change-Id: Ia48ca369701c14d1913d8f7b66ed466b7b840224
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1664319
(cherry picked from commit ac40d082e8)
Reviewed-on: https://git-master.nvidia.com/r/1666445
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2018-02-26 17:01:41 +05:30
committed by mobile promotions
parent df2100018d
commit 37a15ce818
2 changed files with 22 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1,7 +1,7 @@
/*
* GK20A Graphics FIFO (gr host)
*
* Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1647,28 +1647,32 @@ static bool gk20a_fifo_handle_mmu_fault(
* Disable the channel/TSG from hw and increment syncpoints.
*/
if (tsg) {
if (!g->fifo.deferred_reset_pending) {
if (g->fifo.deferred_reset_pending) {
gk20a_disable_tsg(tsg);
} else {
if (!fake_fault)
gk20a_fifo_set_ctx_mmu_error_tsg(g,
tsg);
verbose = gk20a_fifo_error_tsg(g, tsg);
gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
}
gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
/* put back the ref taken early above */
if (refch)
gk20a_channel_put(ch);
} else if (ch) {
if (refch) {
if (!g->fifo.deferred_reset_pending) {
if (g->fifo.deferred_reset_pending) {
g->ops.fifo.disable_channel(ch);
} else {
if (!fake_fault)
gk20a_fifo_set_ctx_mmu_error_ch(
g, refch);
verbose = gk20a_fifo_error_ch(g,
refch);
gk20a_channel_abort(ch, false);
}
gk20a_channel_abort(ch, false);
gk20a_channel_put(ch);
} else {
nvgpu_err(g,

20
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -1049,19 +1049,25 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
#endif
if (tsg) {
if (!g->fifo.deferred_reset_pending &&
rc_type == RC_TYPE_MMU_FAULT)
gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg);
if (g->fifo.deferred_reset_pending) {
gk20a_disable_tsg(tsg);
} else {
if (rc_type == RC_TYPE_MMU_FAULT)
gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg);
gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
}
if (refch)
gk20a_channel_put(refch);
} else if (refch) {
if (!g->fifo.deferred_reset_pending &&
rc_type == RC_TYPE_MMU_FAULT)
if (g->fifo.deferred_reset_pending) {
g->ops.fifo.disable_channel(refch);
} else {
if (rc_type == RC_TYPE_MMU_FAULT)
gk20a_fifo_set_ctx_mmu_error_ch(g, refch);
gk20a_channel_abort(refch, false);
gk20a_channel_abort(refch, false);
}
gk20a_channel_put(refch);
} else {
nvgpu_err(g, "id unknown, abort runlist");