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gpu: nvgpu: remove czf_bypass support

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remove unused czf_bypass support
clean up the czf_bypass from sysfs implementation, gr_gk20a struct,
hal support in gp10b for init_czf_bypass and set_czf_bypass.

Bug 200492671

Change-Id: I2412410838581341c777d07cf4b2fad2d4163956
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070057
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-03-11 13:17:51 -07:00
committed by mobile promotions
parent cb91bf1e13
commit 3856aa54d8
12 changed files with 0 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -198,8 +198,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.disable_rd_coalesce = NULL,
.set_boosted_ctx = NULL,
.set_preemption_mode = vgpu_gr_set_preemption_mode,
.set_czf_bypass = NULL,
.init_czf_bypass = gr_gp10b_init_czf_bypass,
.pre_process_sm_exception = NULL,
.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
.init_preemption_state = NULL,

1
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -217,7 +217,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.disable_rd_coalesce = NULL,
.set_boosted_ctx = NULL,
.set_preemption_mode = vgpu_gr_set_preemption_mode,
.set_czf_bypass = NULL,
.pre_process_sm_exception = NULL,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = NULL,

8
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -2296,10 +2296,6 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
}
#endif
if (g->ops.gr.set_czf_bypass != NULL) {
g->ops.gr.set_czf_bypass(g, c);
}
/* PM ctxt switch is off by default */
gr_ctx->pm_ctx.pm_mode =
g->ops.gr.ctxsw_prog.hw_get_pm_mode_no_ctxsw();
@@ -3095,10 +3091,6 @@ static int gk20a_init_gr_setup_sw(struct gk20a *g)
goto clean_up;
}
if (g->ops.gr.init_czf_bypass != NULL) {
g->ops.gr.init_czf_bypass(g);
}
if (g->ops.gr.init_gfxp_wfi_timeout_count != NULL) {
g->ops.gr.init_gfxp_wfi_timeout_count(g);
}

1
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -224,7 +224,6 @@ struct gr_gk20a {
u32 attrib_cb_gfxp_size;
u32 alpha_cb_default_size;
u32 alpha_cb_size;
u32 czf_bypass;
u32 pd_max_batches;
u32 gfxp_wfi_timeout_count;
u32 gfxp_wfi_timeout_unit;

22
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -2183,28 +2183,6 @@ void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
g->ops.gr.ctxsw_prog.set_full_preemption_ptr(g, mem, gpu_va);
}
void gr_gp10b_init_czf_bypass(struct gk20a *g)
{
g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v();
}
int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch)
{
struct nvgpu_dbg_reg_op ops;
ops.op = REGOP(WRITE_32);
ops.type = REGOP(TYPE_GR_CTX);
ops.status = REGOP(STATUS_SUCCESS);
ops.value_hi = 0;
ops.and_n_mask_lo = gr_gpc0_prop_debug1_czf_bypass_m();
ops.and_n_mask_hi = 0;
ops.offset = gr_gpc0_prop_debug1_r();
ops.value_lo = gr_gpc0_prop_debug1_czf_bypass_f(
g->gr.czf_bypass);
return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false);
}
void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g)
{
struct gr_gk20a *gr = &g->gr;

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -130,8 +130,6 @@ int gp10b_gr_fuse_override(struct gk20a *g);
int gr_gp10b_init_preemption_state(struct gk20a *g);
void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_mem *mem, u64 gpu_va);
int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch);
void gr_gp10b_init_czf_bypass(struct gk20a *g);
void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g);
unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
bool gr_gp10b_suspend_context(struct channel_gk20a *ch,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -342,8 +342,6 @@ static const struct gpu_ops gp10b_ops = {
.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.set_czf_bypass = gr_gp10b_set_czf_bypass,
.init_czf_bypass = gr_gp10b_init_czf_bypass,
.pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
.init_preemption_state = gr_gp10b_init_preemption_state,

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -449,7 +449,6 @@ static const struct gpu_ops gv100_ops = {
.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.set_czf_bypass = NULL,
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = NULL,

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -401,7 +401,6 @@ static const struct gpu_ops gv11b_ops = {
.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.set_czf_bypass = NULL,
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = gr_gv11b_init_preemption_state,

3
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -446,9 +446,6 @@ struct gpu_ops {
int (*resume_from_pause)(struct gk20a *g);
int (*clear_sm_errors)(struct gk20a *g);
u32 (*tpc_enabled_exceptions)(struct gk20a *g);
int (*set_czf_bypass)(struct gk20a *g,
struct channel_gk20a *ch);
void (*init_czf_bypass)(struct gk20a *g);
bool (*sm_debugger_attached)(struct gk20a *g);
void (*suspend_single_sm)(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm,

29
drivers/gpu/nvgpu/os/linux/sysfs.c
View File

@@ -984,33 +984,6 @@ static ssize_t max_timeslice_us_store(struct device *dev,
static DEVICE_ATTR(max_timeslice_us, ROOTRW, max_timeslice_us_read,
max_timeslice_us_store);
static ssize_t czf_bypass_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct gk20a *g = get_gk20a(dev);
unsigned long val;
if (kstrtoul(buf, 10, &val) < 0)
return -EINVAL;
if (val >= 4)
return -EINVAL;
g->gr.czf_bypass = val;
return count;
}
static ssize_t czf_bypass_read(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct gk20a *g = get_gk20a(dev);
return sprintf(buf, "%d\n", g->gr.czf_bypass);
}
static DEVICE_ATTR(czf_bypass, ROOTRW, czf_bypass_read, czf_bypass_store);
static ssize_t pd_max_batches_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
@@ -1201,7 +1174,6 @@ void nvgpu_remove_sysfs(struct device *dev)
nvgpu_nvhost_remove_symlink(get_gk20a(dev));
#endif
device_remove_file(dev, &dev_attr_czf_bypass);
device_remove_file(dev, &dev_attr_pd_max_batches);
device_remove_file(dev, &dev_attr_gfxp_wfi_timeout_count);
device_remove_file(dev, &dev_attr_gfxp_wfi_timeout_unit);
@@ -1256,7 +1228,6 @@ int nvgpu_create_sysfs(struct device *dev)
error |= nvgpu_nvhost_create_symlink(g);
#endif
error |= device_create_file(dev, &dev_attr_czf_bypass);
error |= device_create_file(dev, &dev_attr_pd_max_batches);
error |= device_create_file(dev, &dev_attr_gfxp_wfi_timeout_count);
error |= device_create_file(dev, &dev_attr_gfxp_wfi_timeout_unit);

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -467,7 +467,6 @@ static const struct gpu_ops tu104_ops = {
.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.set_czf_bypass = NULL,
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.init_preemption_state = gr_gv11b_init_preemption_state,