nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 02:52:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: fifo ops for handling sched error and ctxsw timeout

Browse Source 
For t19x, ctxsw timeout is not handled as part of fifo sched error
interrupt. A new fifo interrupt, ctxsw_timeout is added.

Bug 1856152
JIRA GPUT19X-74

Change-Id: I5a2ed15d967e5b14fbbb51b074080f1562bca84c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1317599
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2017-03-08 22:18:36 -08:00
committed by mobile promotions
parent 4c5feb1f72
commit 3867db86bc
4 changed files with 15 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -2051,7 +2051,7 @@ static bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch,
return recover;
}
static bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
bool *verbose, u32 *ms)
{
struct channel_gk20a *ch;
@@ -2121,7 +2121,7 @@ static bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
return recover;
}
static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
bool gk20a_fifo_handle_sched_error(struct gk20a *g)
{
u32 sched_error;
u32 engine_id;
@@ -2205,7 +2205,7 @@ static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr)
}
if (fifo_intr & fifo_intr_0_sched_error_pending_f()) {
print_channel_reset_log = gk20a_fifo_handle_sched_error(g);
print_channel_reset_log = g->ops.fifo.handle_sched_error(g);
handled |= fifo_intr_0_sched_error_pending_f();
}
@@ -2463,6 +2463,9 @@ void gk20a_fifo_isr(struct gk20a *g)
if (fifo_intr & fifo_intr_0_pbdma_intr_pending_f())
clear_intr |= fifo_pbdma_isr(g, fifo_intr);
if (g->ops.fifo.handle_ctxsw_timeout)
g->ops.fifo.handle_ctxsw_timeout(g, fifo_intr);
if (unlikely(fifo_intr & error_intr_mask))
clear_intr = fifo_error_isr(g, fifo_intr);
@@ -4273,4 +4276,5 @@ void gk20a_init_fifo(struct gpu_ops *gops)
gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put;
gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val;
gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
}

5
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -386,4 +386,9 @@ bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids,
u32 hw_id, unsigned int id_type, unsigned int rc_type,
struct mmu_fault_info *mmfault);
bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
bool *verbose, u32 *ms);
bool gk20a_fifo_handle_sched_error(struct gk20a *g);
#endif /*__GR_GK20A_H__*/

2
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -472,6 +472,8 @@ struct gpu_ops {
void (*teardown_ch_tsg)(struct gk20a *g, u32 act_eng_bitmask,
u32 id, unsigned int id_type, unsigned int rc_type,
struct mmu_fault_info *mmfault);
bool (*handle_sched_error)(struct gk20a *g);
bool (*handle_ctxsw_timeout)(struct gk20a *g, u32 fifo_intr);
} fifo;
struct pmu_v {
/*used for change of enum zbc update cmd id from ver 0 to ver1*/

1
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
View File

@@ -228,4 +228,5 @@ void gm20b_init_fifo(struct gpu_ops *gops)
gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs;
gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw;
gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
}