gpu: nvgpu: move dbg_session_ops to gops

Move dbg_session_ops to gops for better code consistency

JIRA VFND-1905

Change-Id: I04a11d77dd8c26d9922e80e556822f80dd2bc36d
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1192641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c

@@ -31,13 +31,6 @@
 #include "hw_gr_gk20a.h"
 #include "hw_perf_gk20a.h"
 
-static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, u32  powermode);
-
-struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a = {
-	.exec_reg_ops = exec_regops_gk20a,
-	.dbg_set_powergate = dbg_set_powergate,
-};
-
 /*
  * API to get first channel from the list of all channels
  * bound to the debug session
@@ -84,7 +77,6 @@ static int alloc_session(struct dbg_session_gk20a **_dbg_s)
 		return -ENOMEM;
 
 	dbg_s->id = generate_session_id();
-	dbg_s->ops = &dbg_gpu_session_ops_gk20a;
 	*_dbg_s = dbg_s;
 	return 0;
 }
@@ -478,7 +470,7 @@ int gk20a_dbg_gpu_dev_release(struct inode *inode, struct file *filp)
 	 * calling powergate/timeout enable ioctl
 	 */
 	mutex_lock(&g->dbg_sessions_lock);
-	dbg_s->ops->dbg_set_powergate(dbg_s,
+	g->ops.dbg_session_ops.dbg_set_powergate(dbg_s,
 				NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE);
 	nvgpu_dbg_timeout_enable(dbg_s, NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE);
 	mutex_unlock(&g->dbg_sessions_lock);
@@ -976,7 +968,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
 
 	gk20a_dbg_fn("%d ops, total size %llu", args->num_ops, ops_size);
 
-	if (!dbg_s->ops) {
+	if (!dbg_s->id) {
 		gk20a_err(dev, "can't call reg_ops on an unbound debugger session");
 		return -EINVAL;
 	}
@@ -1018,16 +1010,18 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
 		/* In the virtual case, the server will handle
 		 * disabling/enabling powergating when processing reg ops
 		 */
-		powergate_err = dbg_s->ops->dbg_set_powergate(dbg_s,
+		powergate_err = g->ops.dbg_session_ops.dbg_set_powergate(dbg_s,
 					NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE);
 		is_pg_disabled = true;
 	}
 
 	if (!powergate_err) {
-		err = dbg_s->ops->exec_reg_ops(dbg_s, ops, args->num_ops);
+		err = g->ops.dbg_session_ops.exec_reg_ops(dbg_s, ops,
+							args->num_ops);
 		/* enable powergate, if previously disabled */
 		if (is_pg_disabled) {
-			powergate_err = dbg_s->ops->dbg_set_powergate(dbg_s,
+			powergate_err =
+				g->ops.dbg_session_ops.dbg_set_powergate(dbg_s,
 					NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE);
 		}
 	}
@@ -1166,7 +1160,7 @@ static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s,
 		      dev_name(dbg_s->dev), args->mode);
 
 	mutex_lock(&g->dbg_sessions_lock);
-	err = dbg_s->ops->dbg_set_powergate(dbg_s, args->mode);
+	err = g->ops.dbg_session_ops.dbg_set_powergate(dbg_s, args->mode);
 	mutex_unlock(&g->dbg_sessions_lock);
 	return  err;
 }
@@ -1404,3 +1398,9 @@ static int gk20a_perfbuf_unmap(struct dbg_session_gk20a *dbg_s,
 
 	return 0;
 }
+
+void gk20a_init_dbg_session_ops(struct gpu_ops *gops)
+{
+	gops->dbg_session_ops.exec_reg_ops = exec_regops_gk20a;
+	gops->dbg_session_ops.dbg_set_powergate = dbg_set_powergate;
+};

drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h

@@ -34,13 +34,6 @@ void gk20a_dbg_gpu_post_events(struct channel_gk20a *fault_ch);
 struct channel_gk20a *
 nvgpu_dbg_gpu_get_session_channel(struct dbg_session_gk20a *dbg_s);
 
-struct dbg_gpu_session_ops {
-	int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s,
-			    struct nvgpu_dbg_gpu_reg_op *ops,
-			    u64 num_ops);
-	int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, u32 mode);
-};
-
 struct dbg_gpu_session_events {
 	wait_queue_head_t wait_queue;
 	bool events_enabled;
@@ -76,9 +69,6 @@ struct dbg_session_gk20a {
 	struct list_head ch_list;
 	struct mutex ch_list_lock;
 
-	/* session operations */
-	struct dbg_gpu_session_ops *ops;
-
 	/* event support */
 	struct dbg_gpu_session_events dbg_events;
 
@@ -98,12 +88,11 @@ struct dbg_session_channel_data {
 	struct dbg_session_data *session_data;
 };
 
-extern struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a;
-
 int dbg_unbind_single_channel_gk20a(struct dbg_session_gk20a *dbg_s,
 			struct dbg_session_channel_data *ch_data);
 
 bool gk20a_dbg_gpu_broadcast_stop_trigger(struct channel_gk20a *ch);
 int gk20a_dbg_gpu_clear_broadcast_stop_trigger(struct channel_gk20a *ch);
+void gk20a_init_dbg_session_ops(struct gpu_ops *gops);
 
 #endif /* DBG_GPU_GK20A_H */

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -628,6 +628,13 @@ struct gpu_ops {
 		void (*show_dump)(struct gk20a *g,
 				struct gk20a_debug_output *o);
 	} debug;
+	struct {
+		int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s,
+			    struct nvgpu_dbg_gpu_reg_op *ops,
+			    u64 num_ops);
+		int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s,
+					u32 mode);
+	} dbg_session_ops;
 	struct {
 		void (*get_program_numbers)(struct gk20a *g,
 					    u32 block_height_log2,

drivers/gpu/nvgpu/gk20a/hal_gk20a.c

@@ -31,6 +31,7 @@
 #include "therm_gk20a.h"
 #include "hw_proj_gk20a.h"
 #include "tsg_gk20a.h"
+#include "dbg_gpu_gk20a.h"
 
 static struct gpu_ops gk20a_ops = {
 	.clock_gating = {
@@ -153,6 +154,7 @@ int gk20a_init_hal(struct gk20a *g)
 	gk20a_init_clk_ops(gops);
 	gk20a_init_regops(gops);
 	gk20a_init_debug_ops(gops);
+	gk20a_init_dbg_session_ops(gops);
 	gk20a_init_therm_ops(gops);
 	gk20a_init_tsg_ops(gops);
 	gops->name = "gk20a";

drivers/gpu/nvgpu/gk20a/regops_gk20a.c

@@ -825,7 +825,8 @@ static int gk20a_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
 	ops[3].offset   = 0x00419f40;
 	ops[3].value_lo = 0x18;
 
-	return dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops));
+	return dbg_s->g->ops.dbg_session_ops.exec_reg_ops(dbg_s, ops,
+							ARRAY_SIZE(ops));
 }
 
 void gk20a_init_regops(struct gpu_ops *gops)

drivers/gpu/nvgpu/gm206/hal_gm206.c

@@ -40,6 +40,7 @@
 #include "bios_gm206.h"
 #include "gr_gm206.h"
 #include "hw_proj_gm206.h"
+#include "gk20a/dbg_gpu_gk20a.h"
 
 static struct gpu_ops gm206_ops = {
 	.clock_gating = {
@@ -194,6 +195,7 @@ int gm206_init_hal(struct gk20a *g)
 	gm20b_init_clk_ops(gops);
 	gm20b_init_regops(gops);
 	gm20b_init_debug_ops(gops);
+	gk20a_init_dbg_session_ops(gops);
 	gm20b_init_cde_ops(gops);
 	gm20b_init_therm_ops(gops);
 	gk20a_init_tsg_ops(gops);

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -35,6 +35,7 @@
 #include "cde_gm20b.h"
 #include "therm_gm20b.h"
 #include "hw_proj_gm20b.h"
+#include "gk20a/dbg_gpu_gk20a.h"
 
 #define FUSE_OPT_PRIV_SEC_DIS_0 0x264
 #define PRIV_SECURITY_DISABLE 0x01
@@ -221,6 +222,7 @@ int gm20b_init_hal(struct gk20a *g)
 	gm20b_init_clk_ops(gops);
 	gm20b_init_regops(gops);
 	gm20b_init_debug_ops(gops);
+	gk20a_init_dbg_session_ops(gops);
 	gm20b_init_cde_ops(gops);
 	gm20b_init_therm_ops(gops);
 	gk20a_init_tsg_ops(gops);

drivers/gpu/nvgpu/vgpu/dbg_vgpu.c

@@ -102,8 +102,8 @@ static int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode)
 	return err;
 }
 
-void vgpu_dbg_init(void)
+void vgpu_init_dbg_session_ops(struct gpu_ops *gops)
 {
-	dbg_gpu_session_ops_gk20a.exec_reg_ops = vgpu_exec_regops;
-	dbg_gpu_session_ops_gk20a.dbg_set_powergate = vgpu_dbg_set_powergate;
+	gops->dbg_session_ops.exec_reg_ops = vgpu_exec_regops;
+	gops->dbg_session_ops.dbg_set_powergate = vgpu_dbg_set_powergate;
 }

drivers/gpu/nvgpu/vgpu/vgpu.c

@@ -348,6 +348,7 @@ void vgpu_init_hal_common(struct gk20a *g)
 	vgpu_init_ltc_ops(gops);
 	vgpu_init_mm_ops(gops);
 	vgpu_init_debug_ops(gops);
+	vgpu_init_dbg_session_ops(gops);
 	vgpu_init_fecs_trace_ops(gops);
 	vgpu_init_tsg_ops(gops);
 	gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics;
@@ -531,7 +532,6 @@ int vgpu_probe(struct platform_device *pdev)
 		return err;
 
 	vgpu_init_support(pdev);
-	vgpu_dbg_init();
 
 	init_rwsem(&gk20a->busy_lock);
 

drivers/gpu/nvgpu/vgpu/vgpu.h

@@ -60,7 +60,7 @@ void vgpu_init_hal_common(struct gk20a *g);
 int vgpu_gk20a_init_hal(struct gk20a *g);
 int vgpu_gm20b_init_hal(struct gk20a *g);
 
-void vgpu_dbg_init(void);
+void vgpu_init_dbg_session_ops(struct gpu_ops *gops);
 #else
 static inline int vgpu_pm_prepare_poweroff(struct device *dev)
 {