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gpu: nvgpu: Add channel.reset_faulted HAL

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Add a HAL op for resetting the eng_faulted and pbdma_faulted states on a
channel. This used to be a local feature in fifo_gv11b.c; the HAL is
defined for all chips from gv11b onwards.

Jira NVGPU-1307

Change-Id: I120a59c429851cc69e712ddd5b06a4b3d16c06c9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017269
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2019-02-12 13:05:27 +02:00
committed by mobile promotions
parent 44e4d69734
commit 38c548a39c
7 changed files with 24 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/nvgpu/common/fifo/channel_gv11b.c
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@@ -65,3 +65,18 @@ void gv11b_channel_read_state(struct gk20a *g, struct channel_gk20a *ch,
state->eng_faulted = ccsr_channel_eng_faulted_v(reg) ==
ccsr_channel_eng_faulted_true_v();
}
void gv11b_channel_reset_faulted(struct gk20a *g, struct channel_gk20a *ch,
bool eng, bool pbdma)
{
u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid));
if (eng) {
reg |= ccsr_channel_eng_faulted_reset_f();
}
if (pbdma) {
reg |= ccsr_channel_pbdma_faulted_reset_f();
}
gk20a_writel(g, ccsr_channel_r(ch->chid), reg);
}

2
drivers/gpu/nvgpu/common/fifo/channel_gv11b.h
View File

@@ -33,5 +33,7 @@ void gv11b_channel_unbind(struct channel_gk20a *ch);
u32 gv11b_channel_count(struct gk20a *g);
void gv11b_channel_read_state(struct gk20a *g, struct channel_gk20a *ch,
struct nvgpu_channel_hw_state *state);
void gv11b_channel_reset_faulted(struct gk20a *g, struct channel_gk20a *ch,
bool eng, bool pbdma);
#endif /* FIFO_CHANNEL_GV11B_H */

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -801,6 +801,7 @@ static const struct gpu_ops gv100_ops = {
.count = gv100_channel_count,
.read_state = gv11b_channel_read_state,
.force_ctx_reload = gm20b_channel_force_ctx_reload,
.reset_faulted = gv11b_channel_reset_faulted,
},
.netlist = {
.get_netlist_name = gv100_netlist_get_name,

23
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -54,7 +54,6 @@
#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
#include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
#include <nvgpu/hw/gv11b/hw_ram_gv11b.h>
#include <nvgpu/hw/gv11b/hw_ccsr_gv11b.h>
#include <nvgpu/hw/gv11b/hw_usermode_gv11b.h>
#include <nvgpu/hw/gv11b/hw_top_gv11b.h>
#include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h>
@@ -589,15 +588,6 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id,
return ret;
}
static void gv11b_reset_eng_faulted_ch(struct gk20a *g, u32 chid)
{
u32 reg_val;
reg_val = gk20a_readl(g, ccsr_channel_r(chid));
reg_val |= ccsr_channel_eng_faulted_reset_f();
gk20a_writel(g, ccsr_channel_r(chid), reg_val);
}
static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg)
{
struct gk20a *g = tsg->g;
@@ -605,20 +595,11 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg)
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
gv11b_reset_eng_faulted_ch(g, ch->chid);
g->ops.channel.reset_faulted(g, ch, true, false);
}
nvgpu_rwsem_up_read(&tsg->ch_list_lock);
}
static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid)
{
u32 reg_val;
reg_val = gk20a_readl(g, ccsr_channel_r(chid));
reg_val |= ccsr_channel_pbdma_faulted_reset_f();
gk20a_writel(g, ccsr_channel_r(chid), reg_val);
}
static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg)
{
struct gk20a *g = tsg->g;
@@ -626,7 +607,7 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg)
nvgpu_rwsem_down_read(&tsg->ch_list_lock);
nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) {
gv11b_reset_pbdma_faulted_ch(g, ch->chid);
g->ops.channel.reset_faulted(g, ch, false, true);
}
nvgpu_rwsem_up_read(&tsg->ch_list_lock);
}

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -760,6 +760,7 @@ static const struct gpu_ops gv11b_ops = {
.count = gv11b_channel_count,
.read_state = gv11b_channel_read_state,
.force_ctx_reload = gm20b_channel_force_ctx_reload,
.reset_faulted = gv11b_channel_reset_faulted,
},
.netlist = {
.get_netlist_name = gv11b_netlist_get_name,

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -911,6 +911,8 @@ struct gpu_ops {
void (*read_state)(struct gk20a *g, struct channel_gk20a *ch,
struct nvgpu_channel_hw_state *state);
void (*force_ctx_reload)(struct channel_gk20a *ch);
void (*reset_faulted)(struct gk20a *g, struct channel_gk20a *ch,
bool eng, bool pbdma);
} channel;
struct pmu_v {
u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -832,6 +832,7 @@ static const struct gpu_ops tu104_ops = {
.count = gv100_channel_count,
.read_state = gv11b_channel_read_state,
.force_ctx_reload = gm20b_channel_force_ctx_reload,
.reset_faulted = gv11b_channel_reset_faulted,
},
.netlist = {
.get_netlist_name = tu104_netlist_get_name,