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gpu: nvgpu: Clear timer registers on bus intr

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Clear error address and code from timer registers. This allows
following errors to report correctly.

Change-Id: I9845ce77347ea7b9231e33f4164098cbb8694ba3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
This commit is contained in:
Terje Bergstrom
2016-08-26 10:21:59 -07:00
committed by mobile promotions
parent 4bd9682c92
commit 39112867cc
1 changed files with 2 additions and 0 deletions
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2
drivers/gpu/nvgpu/gk20a/gk20a.c
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@@ -684,6 +684,8 @@ void gk20a_pbus_isr(struct gk20a *g)
"NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n",
gk20a_readl(g, gr_gpc0_fs_gpc_r()));
gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
}
if (val)