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gpu: nvgpu: Correct laying of terminating WPR HDR

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Termination WPR header is inserted in the non-wpr
blob so that HS knows when to stop processing WPR
headers.

nvgpu_mem_wr32 is copying the terminating WPR header
@ wrong offset in non-wpr blob.

This caused overwriting of the LS signatures present
in the non wpr region, thus leading to LS authentication
failure for GPCCS falcon.

Fix added for t210/t186 as well.

Bug 200362639

Change-Id: I60088b2dd2304fb5de0402b28822b305b34394c2
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594862
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Goyal
2017-11-09 11:19:35 +05:30
committed by mobile promotions
parent d58c3bd152
commit 39527d5885
2 changed files with 14 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -652,10 +652,12 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
struct nvgpu_mem *ucode)
{
struct lsfm_managed_ucode_img *pnode = plsfm->ucode_img_list;
struct lsf_wpr_header last_wpr_hdr;
u32 i;
/* The WPR array is at the base of the WPR */
pnode = plsfm->ucode_img_list;
memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header));
i = 0;
/*
@@ -729,10 +731,11 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
}
/* Tag the terminator WPR header with an invalid falcon ID. */
nvgpu_mem_wr32(g, ucode,
plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header) +
offsetof(struct lsf_wpr_header, falcon_id),
LSF_FALCON_ID_INVALID);
last_wpr_hdr.falcon_id = LSF_FALCON_ID_INVALID;
nvgpu_mem_wr_n(g, ucode,
plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header),
&last_wpr_hdr,
sizeof(struct lsf_wpr_header));
}
/*!

11
drivers/gpu/nvgpu/gp106/acr_gp106.c
View File

@@ -682,10 +682,12 @@ void lsfm_init_wpr_contents(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode)
{
struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list;
struct lsf_wpr_header_v1 last_wpr_hdr;
u32 i;
/* The WPR array is at the base of the WPR */
pnode = plsfm->ucode_img_list;
memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header_v1));
i = 0;
/*
@@ -759,10 +761,11 @@ void lsfm_init_wpr_contents(struct gk20a *g,
}
/* Tag the terminator WPR header with an invalid falcon ID. */
nvgpu_mem_wr32(g, ucode,
plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header_v1) +
offsetof(struct lsf_wpr_header_v1, falcon_id),
LSF_FALCON_ID_INVALID);
last_wpr_hdr.falcon_id = LSF_FALCON_ID_INVALID;
nvgpu_mem_wr_n(g, ucode,
plsfm->managed_flcn_cnt * sizeof(struct lsf_wpr_header_v1),
&last_wpr_hdr,
sizeof(struct lsf_wpr_header_v1));
}
/*!