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gpu: nvgpu: get bios perf and clk table ptr

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Implement support for reading perf and clk tables from VBIOS.

JIRA DNVGPU-83

Change-Id: I095fea08479161362e4c2ffa7500ee6a57d6d447
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1202602
(cherry picked from commit fb7c7356f131a198bd655a25fc6ff17067477e1b)
Reviewed-on: http://git-master/r/1217299
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2016-07-18 14:47:20 +05:30
committed by mobile promotions
parent f56ed459dd
commit 39c48cb8bf
3 changed files with 74 additions and 7 deletions
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5
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -53,6 +53,7 @@ struct acr_desc;
#include "cde_gk20a.h"
#include "debug_gk20a.h"
#include "sched_gk20a.h"
#include "gm206/bios_gm206.h"
/* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds.
32 ns is the resolution of ptimer. */
@@ -656,6 +657,8 @@ struct gpu_ops {
struct {
int (*init)(struct gk20a *g);
void *(*get_perf_table_ptrs)(struct gk20a *g,
struct bit_token *ptoken, u8 table_id);
} bios;
#if defined(CONFIG_GK20A_CYCLE_STATS)
struct {
@@ -704,6 +707,8 @@ struct nvgpu_bios {
u32 devinit_tables_phys_base;
u32 devinit_script_phys_base;
struct bit_token *perf_token;
struct bit_token *clock_token;
u32 expansion_rom_offset;
};

55
drivers/gpu/nvgpu/gm206/bios_gm206.c
View File

@@ -21,6 +21,7 @@
#include "hw_mc_gm206.h"
#include "hw_xve_gm206.h"
#include "hw_top_gm206.h"
#include "bios_gm206.h"
#define BIT_HEADER_ID 0xb8ff
#define BIT_HEADER_SIGNATURE 0x00544942
@@ -54,15 +55,10 @@ struct bit {
u8 header_checksum;
} __packed;
struct bit_token {
u8 token_id;
u8 data_version;
u16 data_size;
u16 data_ptr;
} __packed;
#define TOKEN_ID_NVINIT_PTRS 0x49
#define TOKEN_ID_FALCON_DATA 0x70
#define TOKEN_ID_PERF_PTRS 0x50
#define TOKEN_ID_CLOCK_PTRS 0x43
struct nvinit_ptrs {
u16 initscript_table_ptr;
@@ -423,6 +419,42 @@ static void gm206_bios_parse_falcon_data_v2(struct gk20a *g, int offset)
"could not parse falcon ucode table");
}
static void *gm206_bios_get_perf_table_ptrs(struct gk20a *g,
struct bit_token *ptoken, u8 table_id)
{
u32 perf_table_id_offset = 0;
u8 *perf_table_ptr = NULL;
if (ptoken != NULL &&
table_id < (ptoken->data_size/sizeof(u32))) {
perf_table_id_offset = *((u32 *)&g->bios.data[
ptoken->data_ptr +
(table_id * PERF_PTRS_WIDTH)]);
gk20a_dbg_info("Perf_Tbl_ID-offset 0x%x Tbl_ID_Ptr-offset- 0x%x",
(ptoken->data_ptr +
(table_id * PERF_PTRS_WIDTH)),
perf_table_id_offset);
if (perf_table_id_offset != 0) {
/* check is perf_table_id_offset is > 64k */
if (perf_table_id_offset & ~0xFFFF)
perf_table_ptr =
&g->bios.data[g->bios.expansion_rom_offset +
perf_table_id_offset];
else
perf_table_ptr =
&g->bios.data[perf_table_id_offset];
} else
gk20a_warn(g->dev, "PERF TABLE ID %d is NULL",
table_id);
} else
gk20a_warn(g->dev, "INVALID PERF TABLE ID - %d ", table_id);
return (void *)perf_table_ptr;
}
static void gm206_bios_parse_bit(struct gk20a *g, int offset)
{
struct bit bit;
@@ -453,6 +485,14 @@ static void gm206_bios_parse_bit(struct gk20a *g, int offset)
gm206_bios_parse_falcon_data_v2(g,
bit_token.data_ptr);
break;
case TOKEN_ID_PERF_PTRS:
g->bios.perf_token =
(struct bit_token *)&g->bios.data[offset];
break;
case TOKEN_ID_CLOCK_PTRS:
g->bios.clock_token =
(struct bit_token *)&g->bios.data[offset];
break;
default:
break;
}
@@ -715,4 +755,5 @@ static int gm206_bios_init(struct gk20a *g)
void gm206_init_bios(struct gpu_ops *gops)
{
gops->bios.init = gm206_bios_init;
gops->bios.get_perf_table_ptrs = gm206_bios_get_perf_table_ptrs;
}

21
drivers/gpu/nvgpu/gm206/bios_gm206.h
View File

@@ -13,6 +13,27 @@
#ifndef NVGPU_BIOS_GM206_H
#define NVGPU_BIOS_GM206_H
#define PERF_PTRS_WIDTH 0x4
enum {
CLOCKS_TABLE = 2,
CLOCK_PROGRAMMING_TABLE,
NAFLL_TABLE,
ADC_TABLE,
};
enum {
CONTINUOUS_VIRTUAL_BINNING_TABLE,
};
struct bit_token {
u8 token_id;
u8 data_version;
u16 data_size;
u16 data_ptr;
} __packed;
struct gpu_ops;
void gm206_init_bios(struct gpu_ops *gops);