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gpu: nvgpu: Move gk20a clock helper functions to common file

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This allows us to use these functions with both Tegra and Common Clock
Frameworks

Bug 200233943

Change-Id: I5a394d7bacfecabeabc64d32dab214d2e7cf89d7
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1242481
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Peter Boonstoppel
2016-10-25 13:54:51 -07:00
committed by mobile promotions
parent 30de7ab4f7
commit 3a6d47db9d
3 changed files with 63 additions and 42 deletions
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3
drivers/gpu/nvgpu/Makefile.nvgpu
View File

@@ -119,7 +119,8 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
nvgpu-$(CONFIG_TEGRA_CLK_FRAMEWORK) += \
gm20b/clk_gm20b.o \
gk20a/clk_gk20a.o
gk20a/clk_gk20a.o \
clk/clk_common.o
nvgpu-$(CONFIG_GK20A_DEVFREQ) += \
gk20a/gk20a_scale.o

61
drivers/gpu/nvgpu/clk/clk_common.c Normal file
View File

@@ -0,0 +1,61 @@
/*
* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include "gk20a/gk20a.h"
struct clk *gk20a_clk_get(struct gk20a *g)
{
if (!g->clk.tegra_clk) {
struct clk *clk;
char clk_dev_id[32];
struct device *dev = dev_from_gk20a(g);
snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev));
clk = clk_get_sys(clk_dev_id, "gpu");
if (IS_ERR(clk)) {
gk20a_err(dev, "fail to get tegra gpu clk %s/gpu\n",
clk_dev_id);
return NULL;
}
g->clk.tegra_clk = clk;
}
return g->clk.tegra_clk;
}
unsigned long gk20a_clk_get_rate(struct gk20a *g)
{
struct clk_gk20a *clk = &g->clk;
return rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
}
long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate)
{
/* make sure the clock is available */
if (!gk20a_clk_get(g))
return rate;
return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate);
}
int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate)
{
return clk_set_rate(g->clk.tegra_clk, rate);
}

41
drivers/gpu/nvgpu/gk20a/clk_gk20a.c
View File

@@ -412,27 +412,6 @@ static int gk20a_init_clk_reset_enable_hw(struct gk20a *g)
return 0;
}
struct clk *gk20a_clk_get(struct gk20a *g)
{
if (!g->clk.tegra_clk) {
struct clk *clk;
char clk_dev_id[32];
struct device *dev = dev_from_gk20a(g);
snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev));
clk = clk_get_sys(clk_dev_id, "gpu");
if (IS_ERR(clk)) {
gk20a_err(dev, "fail to get tegra gpu clk %s/gpu\n",
clk_dev_id);
return NULL;
}
g->clk.tegra_clk = clk;
}
return g->clk.tegra_clk;
}
static int gk20a_init_clk_setup_sw(struct gk20a *g)
{
struct clk_gk20a *clk = &g->clk;
@@ -709,26 +688,6 @@ void gk20a_init_clk_ops(struct gpu_ops *gops)
gops->clk.suspend_clk_support = gk20a_suspend_clk_support;
}
unsigned long gk20a_clk_get_rate(struct gk20a *g)
{
struct clk_gk20a *clk = &g->clk;
return rate_gpc2clk_to_gpu(clk->gpc_pll.freq);
}
long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate)
{
/* make sure the clock is available */
if (!gk20a_clk_get(g))
return rate;
return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate);
}
int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate)
{
return clk_set_rate(g->clk.tegra_clk, rate);
}
#ifdef CONFIG_DEBUG_FS
static int rate_get(void *data, u64 *val)