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gpu: nvgpu: fix tpc exception enablement

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Use read modify write to enable sm exception. This is to avoid
disabling alredy enabled interrupts e.g. tex etc.

JIRA GPUT19X-69

Change-Id: I94f75f9a37310a8271193b4996e9b4b2ba29e4ae
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515914
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Seema Khowala
2017-07-09 14:05:57 -07:00
committed by mobile promotions
parent 961e98aa11
commit 3bc7e4aadd
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -8398,14 +8398,16 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state)
int gr_gk20a_resume_from_pause(struct gk20a *g)
{
int err = 0;
u32 reg_val;
/* Clear the pause mask to tell the GPU we want to resume everyone */
gk20a_writel(g,
gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(), 0);
/* explicitly re-enable forwarding of SM interrupts upon any resume */
gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(),
gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f());
reg_val = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_en_r());
reg_val |= gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f();
gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), reg_val);
/* Now resume all sms, write a 0 to the stop trigger
* then a 1 to the run trigger */