gpu: nvgpu: Disable fault mthd buf intrs on safety

Below CE interrupts are disabled on safety build as fault and
switch mechanism is not supported on safety:
NV_CE_LCE_INTR_STATUS_MTHD_BUFFER_FAULT
NV_CE_LCE_INTR_STATUS_FBUF_CRC_FAIL
NV_CE_LCE_INTR_STATUS_FBUF_MAGIC_CHK_FAIL

Bug 3548082

Change-Id: I400cd02a8c9888b7ef0d71bbc1f7d792b48e8227
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2679052
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/ce/ce_ga10b_fusa.c

@@ -38,19 +38,19 @@
 static u32 ce_lce_intr_mask(void)
 {
 	/* Note: Poison error(fault containment) is not supported on GA10b. */
-	u32 mask = ce_lce_intr_en_launcherr_m() |
+	u32 mask =
+#ifdef CONFIG_NVGPU_NONSTALL_INTR
+		ce_lce_intr_en_nonblockpipe_m() |
+#endif
 #ifdef CONFIG_NVGPU_HAL_NON_FUSA
 		ce_lce_intr_en_stalling_debug_m() |
 		ce_lce_intr_en_blockpipe_m() |
 		ce_lce_intr_en_invalid_config_m() |
-#endif
-#ifdef CONFIG_NVGPU_NONSTALL_INTR
-		ce_lce_intr_en_nonblockpipe_m() |
-#endif
 		ce_lce_intr_en_mthd_buffer_fault_m() |
 		ce_lce_intr_en_fbuf_crc_fail_m() |
-		ce_lce_intr_en_fbuf_magic_chk_fail_m();
-
+		ce_lce_intr_en_fbuf_magic_chk_fail_m() |
+#endif
+		ce_lce_intr_en_launcherr_m();
 	return mask;
 }
 
@@ -192,6 +192,7 @@ void ga10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 	nvgpu_log(g, gpu_dbg_intr, "ce(%u) isr 0x%08x 0x%08x", inst_id,
 			ce_intr, inst_id);
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	/*
 	 * Mismatch between the CRC entry in fault buffer and the
 	 * CRC computed from the methods in the buffer.
@@ -212,7 +213,6 @@ void ga10b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 		clear_intr |= ce_intr_status_fbuf_magic_chk_fail_reset_f();
 	}
 
-#ifdef CONFIG_NVGPU_HAL_NON_FUSA
 	/*
 	 * The stalling_debug error interrupt is triggered when SW writes TRUE
 	 * to NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_STALLING.

drivers/gpu/nvgpu/hal/ce/ce_gp10b.c

@@ -1,7 +1,7 @@
 /*
  * Pascal GPU series Copy Engine.
  *
- * Copyright (c) 2011-2022, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),

drivers/gpu/nvgpu/hal/ce/ce_gv11b_fusa.c

@@ -67,7 +67,6 @@ void gv11b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 		nvgpu_err(g, "ce: inst %d: invalid config", inst_id);
 		clear_intr |= ce_intr_status_invalid_config_reset_f();
 	}
-#endif
 
 	/*
 	 * A MTHD_BUFFER_FAULT interrupt will be triggered if any access
@@ -81,6 +80,7 @@ void gv11b_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
 		nvgpu_err(g, "ce: inst %d: mthd buffer fault", inst_id);
 		clear_intr |= ce_intr_status_mthd_buffer_fault_reset_f();
 	}
+#endif
 
 	nvgpu_writel(g, ce_intr_status_r(inst_id), clear_intr);
 

drivers/gpu/nvgpu/hal/cic/mon/lut_ga10b_fusa.c

@@ -627,6 +627,7 @@ struct nvgpu_err_hw_module ga10b_err_lut[] = {
 					INJECT_SW,
 					NULL, NULL,
 					NULL, NULL, 0, 0),
+#ifdef CONFIG_NVGPU_NON_FUSA
 			GPU_CRITERR("ce_method_buffer_fault",
 					GPU_CE_METHOD_BUFFER_FAULT,
 					INJECT_SW,
@@ -642,7 +643,6 @@ struct nvgpu_err_hw_module ga10b_err_lut[] = {
 					INJECT_NONE,
 					NULL, NULL,
 					NULL, NULL, 0, 0),
-#ifdef CONFIG_NVGPU_NON_FUSA
 			GPU_CRITERR("ce_invalid_config",
 					GPU_CE_INVALID_CONFIG,
 					INJECT_SW,

drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h

@@ -300,10 +300,10 @@ struct mmu_fault_info;
  * @{
  */
 #define GPU_CE_LAUNCH_ERROR			(0x0)
+#ifdef CONFIG_NVGPU_NON_FUSA
 #define GPU_CE_METHOD_BUFFER_FAULT		(0x1)
 #define GPU_CE_FBUF_CRC_FAIL			(0x2)
 #define GPU_CE_FBUF_MAGIC_CHK_FAIL		(0x3)
-#ifdef CONFIG_NVGPU_NON_FUSA
 #define GPU_CE_INVALID_CONFIG			(0x4)
 #endif
 /**

userspace/units/ce/nvgpu-ce.c

@@ -207,8 +207,8 @@ int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args)
 	g->ops.ce.isr_stall = gv11b_ce_stall_isr;
 	for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
 		intr_status_written[inst_id] = 0;
-		/* all intr sources except (non)blockpipe as they are not supported on safety */
-		intr_val = 0x14;
+		/* all intr sources except launcherr as they are not supported on safety */
+		intr_val = 0x4;
 		nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
 						intr_val);
 		g->ops.ce.isr_stall(g, inst_id, 0);