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gpu: nvgpu: define runlist level in common code

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All the runlist levels NVGPU_RUNLIST_INTERLEAVE_LEVEL_* are declared in linux
specific uapi header and used in common code
But since common code should be linux-independent, move these uses out of
common code

Define new runlist levels NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* in common code
and use them wherever required

Add new API nvgpu_get_common_runlist_level() to get common runlist level of
the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* from linux specific runlist
level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_*

Jira NVGPU-259

Change-Id: Ic19239f0f8275683d5d1b981df530acd90e6dfbb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594327
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2017-11-08 01:57:14 -08:00
committed by mobile promotions
parent c22a5af913
commit 3cb65f57d5
7 changed files with 66 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

55
drivers/gpu/nvgpu/common/linux/ioctl_channel.c
View File

@@ -914,6 +914,48 @@ clean_up:
return ret;
}
/*
* Convert linux specific runlist level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_*
* to common runlist level of the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_*
*/
u32 nvgpu_get_common_runlist_level(u32 level)
{
switch (level) {
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM;
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH;
default:
pr_err("%s: incorrect runlist level\n", __func__);
}
return level;
}
static int gk20a_ioctl_channel_set_runlist_interleave(struct channel_gk20a *ch,
u32 level)
{
int err = 0;
err = gk20a_busy(ch->g);
if (err) {
nvgpu_err(ch->g, "failed to power on, %d", err);
goto fail;
}
level = nvgpu_get_common_runlist_level(level);
err = gk20a_channel_set_runlist_interleave(ch, level);
gk20a_idle(ch->g);
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_runlist_interleave, ch);
fail:
return err;
}
long gk20a_channel_ioctl(struct file *filp,
unsigned int cmd, unsigned long arg)
{
@@ -1202,19 +1244,8 @@ long gk20a_channel_ioctl(struct file *filp,
(struct nvgpu_channel_wdt_args *)buf);
break;
case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE:
err = gk20a_busy(ch->g);
if (err) {
dev_err(dev,
"%s: failed to host gk20a for ioctl cmd: 0x%x",
__func__, cmd);
break;
}
err = gk20a_channel_set_runlist_interleave(ch,
err = gk20a_ioctl_channel_set_runlist_interleave(ch,
((struct nvgpu_runlist_interleave_args *)buf)->level);
gk20a_idle(ch->g);
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_runlist_interleave, ch);
break;
case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE:
err = gk20a_busy(ch->g);

1
drivers/gpu/nvgpu/common/linux/ioctl_channel.h
View File

@@ -31,4 +31,5 @@ extern const struct file_operations gk20a_event_id_ops;
extern const struct file_operations gk20a_channel_ops;
u32 nvgpu_event_id_to_ioctl_channel_event_id(u32 event_id);
u32 nvgpu_get_common_runlist_level(u32 level);
#endif

4
drivers/gpu/nvgpu/common/linux/ioctl_tsg.c
View File

@@ -328,6 +328,7 @@ static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
{
struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
struct gk20a_sched_ctrl *sched = &l->sched_ctrl;
u32 level = arg->level;
int err;
gk20a_dbg(gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid);
@@ -343,7 +344,8 @@ static int gk20a_tsg_ioctl_set_runlist_interleave(struct gk20a *g,
goto done;
}
err = gk20a_tsg_set_runlist_interleave(tsg, arg->level);
level = nvgpu_get_common_runlist_level(level);
err = gk20a_tsg_set_runlist_interleave(tsg, level);
gk20a_idle(g);
done:

8
drivers/gpu/nvgpu/gk20a/channel_gk20a.c
View File

@@ -322,9 +322,9 @@ int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch,
}
switch (level) {
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
ret = g->ops.fifo.set_runlist_interleave(g, ch->chid,
false, 0, level);
break;
@@ -858,7 +858,7 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
ch->has_timedout = false;
ch->wdt_enabled = true;
ch->obj_class = 0;
ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW;
ch->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
ch->timeslice_us = g->timeslice_low_priority_us;
#ifdef CONFIG_TEGRA_19x_GPU
memset(&ch->t19x, 0, sizeof(struct channel_t19x));

8
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -3048,7 +3048,7 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
bool prev_empty,
u32 *entries_left)
{
bool last_level = cur_level == NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH;
bool last_level = cur_level == NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH;
struct channel_gk20a *ch;
bool skip_next = false;
u32 chid, tsgid, count = 0;
@@ -4081,13 +4081,13 @@ u32 gk20a_fifo_pbdma_acquire_val(u64 timeout)
const char *gk20a_fifo_interleave_level_name(u32 interleave_level)
{
switch (interleave_level) {
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
return "LOW";
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
return "MEDIUM";
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
return "HIGH";
default:

7
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -38,6 +38,13 @@
struct gk20a_debug_output;
struct mmu_fault_info;
enum {
NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW = 0,
NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM,
NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH,
NVGPU_FIFO_RUNLIST_INTERLEAVE_NUM_LEVELS,
};
#define MAX_RUNLIST_BUFFERS 2
#define FIFO_INVAL_ENGINE_ID ((u32)~0)

8
drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
View File

@@ -229,9 +229,9 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level)
gk20a_dbg(gpu_dbg_sched, "tsgid=%u interleave=%u", tsg->tsgid, level);
switch (level) {
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH:
ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid,
true, 0, level);
if (!ret)
@@ -304,7 +304,7 @@ struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g)
tsg->tsg_gr_ctx = NULL;
tsg->vm = NULL;
tsg->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW;
tsg->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
tsg->timeslice_us = 0;
tsg->timeslice_timeout = 0;
tsg->timeslice_scale = 0;