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gpu: nvgpu: define runlist level in common code

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All the runlist levels NVGPU_RUNLIST_INTERLEAVE_LEVEL_* are declared in linux
specific uapi header and used in common code
But since common code should be linux-independent, move these uses out of
common code

Define new runlist levels NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* in common code
and use them wherever required

Add new API nvgpu_get_common_runlist_level() to get common runlist level of
the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* from linux specific runlist
level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_*

Jira NVGPU-259

Change-Id: Ic19239f0f8275683d5d1b981df530acd90e6dfbb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594327
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2017-11-08 01:57:14 -08:00
committed by mobile promotions
parent c22a5af913
commit 3cb65f57d5
7 changed files with 66 additions and 25 deletions
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55
drivers/gpu/nvgpu/common/linux/ioctl_channel.c
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@@ -914,6 +914,48 @@ clean_up:
return ret;
}
/*
* Convert linux specific runlist level of the form NVGPU_RUNLIST_INTERLEAVE_LEVEL_*
* to common runlist level of the form NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_*
*/
u32 nvgpu_get_common_runlist_level(u32 level)
{
switch (level) {
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW:
return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW;
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM:
return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM;
case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH:
return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH;
default:
pr_err("%s: incorrect runlist level\n", __func__);
}
return level;
}
static int gk20a_ioctl_channel_set_runlist_interleave(struct channel_gk20a *ch,
u32 level)
{
int err = 0;
err = gk20a_busy(ch->g);
if (err) {
nvgpu_err(ch->g, "failed to power on, %d", err);
goto fail;
}
level = nvgpu_get_common_runlist_level(level);
err = gk20a_channel_set_runlist_interleave(ch, level);
gk20a_idle(ch->g);
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_runlist_interleave, ch);
fail:
return err;
}
long gk20a_channel_ioctl(struct file *filp,
unsigned int cmd, unsigned long arg)
{
@@ -1202,19 +1244,8 @@ long gk20a_channel_ioctl(struct file *filp,
(struct nvgpu_channel_wdt_args *)buf);
break;
case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE:
err = gk20a_busy(ch->g);
if (err) {
dev_err(dev,
"%s: failed to host gk20a for ioctl cmd: 0x%x",
__func__, cmd);
break;
}
err = gk20a_channel_set_runlist_interleave(ch,
err = gk20a_ioctl_channel_set_runlist_interleave(ch,
((struct nvgpu_runlist_interleave_args *)buf)->level);
gk20a_idle(ch->g);
gk20a_channel_trace_sched_param(
trace_gk20a_channel_set_runlist_interleave, ch);
break;
case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE:
err = gk20a_busy(ch->g);