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gpu: nvgpu: delete unused file
File tu104/gr_tu104.c was added with commit f56874aec2 owing to
incorrect conflict resolution. Delete it.
Bug 200447167
Change-Id: I24648a3130bc76731c888328d5742229f6f6c928
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2371610
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
committed by
mobile promotions
mobile promotions
parent
f56874aec2
commit
3d4a70a4b9
@@ -1,549 +0,0 @@
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<<<<<<< HEAD (bbef4c gpu: nvgpu: initialize masks for the perfmon counters 3)
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=======
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/io.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/netlist.h>
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#include "gk20a/gr_gk20a.h"
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#include "gk20a/gr_pri_gk20a.h"
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#include "gp10b/gr_gp10b.h"
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#include "gv11b/gr_gv11b.h"
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#include "tu104/gr_tu104.h"
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#include <nvgpu/hw/tu104/hw_gr_tu104.h>
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bool gr_tu104_is_valid_class(struct gk20a *g, u32 class_num)
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{
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nvgpu_speculation_barrier();
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switch (class_num) {
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case TURING_CHANNEL_GPFIFO_A:
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case TURING_A:
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case TURING_COMPUTE_A:
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case TURING_DMA_COPY_A:
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return true;
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default:
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break;
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}
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return gr_gv11b_is_valid_class(g, class_num);
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};
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bool gr_tu104_is_valid_gfx_class(struct gk20a *g, u32 class_num)
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{
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nvgpu_speculation_barrier();
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switch (class_num) {
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case TURING_A:
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return true;
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default:
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break;
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}
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return gr_gv11b_is_valid_gfx_class(g, class_num);
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}
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bool gr_tu104_is_valid_compute_class(struct gk20a *g, u32 class_num)
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{
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nvgpu_speculation_barrier();
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switch (class_num) {
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case TURING_COMPUTE_A:
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return true;
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default:
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break;
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}
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return gr_gv11b_is_valid_compute_class(g, class_num);
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}
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int gr_tu104_init_sw_bundle64(struct gk20a *g)
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{
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u32 i;
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u32 last_bundle_data_lo = 0;
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u32 last_bundle_data_hi = 0;
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int err = 0;
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struct netlist_av64_list *sw_bundle64_init =
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&g->netlist_vars->sw_bundle64_init;
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for (i = 0U; i < sw_bundle64_init->count; i++) {
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if (i == 0U ||
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(last_bundle_data_lo != sw_bundle64_init->l[i].value_lo) ||
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(last_bundle_data_hi != sw_bundle64_init->l[i].value_hi)) {
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nvgpu_writel(g, gr_pipe_bundle_data_r(),
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sw_bundle64_init->l[i].value_lo);
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nvgpu_writel(g, gr_pipe_bundle_data_hi_r(),
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sw_bundle64_init->l[i].value_hi);
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last_bundle_data_lo = sw_bundle64_init->l[i].value_lo;
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last_bundle_data_hi = sw_bundle64_init->l[i].value_hi;
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}
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nvgpu_writel(g, gr_pipe_bundle_address_r(),
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sw_bundle64_init->l[i].addr);
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if (gr_pipe_bundle_address_value_v(sw_bundle64_init->l[i].addr)
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== GR_GO_IDLE_BUNDLE) {
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err = gr_gk20a_wait_idle(g,
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gk20a_get_gr_idle_timeout(g),
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GR_IDLE_CHECK_DEFAULT);
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} else if (nvgpu_platform_is_silicon(g)) {
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err = gr_gk20a_wait_fe_idle(g,
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gk20a_get_gr_idle_timeout(g),
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GR_IDLE_CHECK_DEFAULT);
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}
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if (err != 0) {
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break;
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}
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}
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return err;
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}
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int gr_tu104_alloc_global_ctx_buffers(struct gk20a *g)
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{
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int err;
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struct gr_gk20a *gr = &g->gr;
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u32 rtv_circular_buffer_size;
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nvgpu_log_fn(g, " ");
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rtv_circular_buffer_size =
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(gr_scc_rm_rtv_cb_size_div_256b_default_f() +
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gr_scc_rm_rtv_cb_size_div_256b_db_adder_f()) *
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gr_scc_bundle_cb_size_div_256b_byte_granularity_v();
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nvgpu_log_info(g, "rtv_circular_buffer_size : %u",
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rtv_circular_buffer_size);
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err = gk20a_gr_alloc_ctx_buffer(g,
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&gr->global_ctx_buffer[RTV_CIRCULAR_BUFFER],
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rtv_circular_buffer_size);
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if (err != 0) {
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return err;
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}
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err = gr_gk20a_alloc_global_ctx_buffers(g);
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if (err != 0) {
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goto clean_up;
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}
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return 0;
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clean_up:
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nvgpu_err(g, "fail");
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gk20a_gr_destroy_ctx_buffer(g,
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&gr->global_ctx_buffer[RTV_CIRCULAR_BUFFER]);
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return err;
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}
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int gr_tu104_map_global_ctx_buffers(struct gk20a *g, struct vm_gk20a *vm,
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struct nvgpu_gr_ctx *gr_ctx, bool vpr)
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{
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int err;
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u64 *g_bfr_va;
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u64 *g_bfr_size;
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int *g_bfr_index;
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struct gr_gk20a *gr = &g->gr;
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struct nvgpu_mem *mem;
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u64 gpu_va;
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nvgpu_log_fn(g, " ");
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g_bfr_va = gr_ctx->global_ctx_buffer_va;
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g_bfr_size = gr_ctx->global_ctx_buffer_size;
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g_bfr_index = gr_ctx->global_ctx_buffer_index;
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/* RTV circular buffer */
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mem = &gr->global_ctx_buffer[RTV_CIRCULAR_BUFFER].mem;
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gpu_va = nvgpu_gmmu_map(vm, mem, mem->size, 0,
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gk20a_mem_flag_none, true, mem->aperture);
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if (gpu_va == 0ULL) {
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return -ENOMEM;
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}
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g_bfr_va[RTV_CIRCULAR_BUFFER_VA] = gpu_va;
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g_bfr_size[RTV_CIRCULAR_BUFFER_VA] = mem->size;
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g_bfr_index[RTV_CIRCULAR_BUFFER_VA] = RTV_CIRCULAR_BUFFER;
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err = gr_gk20a_map_global_ctx_buffers(g, vm, gr_ctx, vpr);
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if (err != 0) {
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goto clean_up;
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}
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return 0;
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clean_up:
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nvgpu_err(g, "fail");
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nvgpu_gmmu_unmap(vm, mem, gpu_va);
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return err;
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}
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static void gr_tu104_commit_rtv_circular_buffer(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx,
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u64 addr, u32 size, u32 gfxpAddSize, bool patch)
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{
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gr_gk20a_ctx_patch_write(g, gr_ctx, gr_scc_rm_rtv_cb_base_r(),
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gr_scc_rm_rtv_cb_base_addr_39_8_f(addr), patch);
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gr_gk20a_ctx_patch_write(g, gr_ctx, gr_scc_rm_rtv_cb_size_r(),
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gr_scc_rm_rtv_cb_size_div_256b_f(size), patch);
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gr_gk20a_ctx_patch_write(g, gr_ctx, gr_gpcs_gcc_rm_rtv_cb_base_r(),
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gr_gpcs_gcc_rm_rtv_cb_base_addr_39_8_f(addr), patch);
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gr_gk20a_ctx_patch_write(g, gr_ctx, gr_scc_rm_gfxp_reserve_r(),
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gr_scc_rm_gfxp_reserve_rtv_cb_size_div_256b_f(gfxpAddSize),
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patch);
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}
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int gr_tu104_commit_global_ctx_buffers(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, bool patch)
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{
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int err;
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u64 addr;
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u32 size;
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u32 gfxpaddsize = 0;
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nvgpu_log_fn(g, " ");
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err = gr_gk20a_commit_global_ctx_buffers(g, gr_ctx, patch);
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if (err != 0) {
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return err;
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}
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if (patch) {
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int err;
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err = gr_gk20a_ctx_patch_write_begin(g, gr_ctx, false);
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if (err != 0) {
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return err;
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}
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}
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/* RTV circular buffer */
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addr = gr_ctx->global_ctx_buffer_va[RTV_CIRCULAR_BUFFER_VA] >>
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U64(gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f());
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size = (gr_scc_rm_rtv_cb_size_div_256b_default_f() +
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gr_scc_rm_rtv_cb_size_div_256b_db_adder_f());
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gr_tu104_commit_rtv_circular_buffer(g, gr_ctx, addr, size,
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gfxpaddsize, patch);
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if (patch) {
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gr_gk20a_ctx_patch_write_end(g, gr_ctx, false);
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}
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return 0;
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}
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int gr_tu104_alloc_gfxp_rtv_cb(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, struct vm_gk20a *vm)
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{
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int err;
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u32 rtv_cb_size;
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nvgpu_log_fn(g, " ");
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rtv_cb_size =
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(gr_scc_rm_rtv_cb_size_div_256b_default_f() +
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gr_scc_rm_rtv_cb_size_div_256b_db_adder_f() +
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gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f()) *
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gr_scc_rm_rtv_cb_size_div_256b_byte_granularity_v();
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err = gr_gp10b_alloc_buffer(vm,
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rtv_cb_size,
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&gr_ctx->gfxp_rtvcb_ctxsw_buffer);
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return err;
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}
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void gr_tu104_commit_gfxp_rtv_cb(struct gk20a *g,
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struct nvgpu_gr_ctx *gr_ctx, bool patch)
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{
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u64 addr;
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u32 rtv_cb_size;
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u32 gfxp_addr_size;
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nvgpu_log_fn(g, " ");
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rtv_cb_size =
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(gr_scc_rm_rtv_cb_size_div_256b_default_f() +
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gr_scc_rm_rtv_cb_size_div_256b_db_adder_f() +
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gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f());
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gfxp_addr_size = gr_scc_rm_rtv_cb_size_div_256b_gfxp_adder_f();
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/* GFXP RTV circular buffer */
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addr = (u64)(u64_lo32(gr_ctx->gfxp_rtvcb_ctxsw_buffer.gpu_va) >>
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gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f()) |
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(u64)(u64_hi32(gr_ctx->gfxp_rtvcb_ctxsw_buffer.gpu_va) <<
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(32U - gr_scc_rm_rtv_cb_base_addr_39_8_align_bits_f()));
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gr_tu104_commit_rtv_circular_buffer(g, gr_ctx, addr,
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rtv_cb_size,
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gfxp_addr_size,
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patch);
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}
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void gr_tu104_bundle_cb_defaults(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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gr->bundle_cb_default_size =
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gr_scc_bundle_cb_size_div_256b__prod_v();
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gr->min_gpm_fifo_depth =
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gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v();
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gr->bundle_cb_token_limit =
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gr_pd_ab_dist_cfg2_token_limit_init_v();
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}
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void gr_tu104_cb_size_default(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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if (gr->attrib_cb_default_size == 0U) {
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gr->attrib_cb_default_size =
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gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
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}
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gr->alpha_cb_default_size =
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gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
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gr->attrib_cb_gfxp_default_size =
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gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
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gr->attrib_cb_gfxp_size =
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gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
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}
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void gr_tu104_free_gr_ctx(struct gk20a *g,
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struct vm_gk20a *vm, struct nvgpu_gr_ctx *gr_ctx)
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{
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nvgpu_log_fn(g, " ");
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if (gr_ctx != NULL) {
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nvgpu_dma_unmap_free(vm, &gr_ctx->gfxp_rtvcb_ctxsw_buffer);
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}
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gr_gk20a_free_gr_ctx(g, vm, gr_ctx);
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}
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void gr_tu104_enable_gpc_exceptions(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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u32 tpc_mask;
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gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(),
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gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f());
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tpc_mask =
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gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->max_tpc_per_gpc_count) - 1);
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gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(),
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(tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) |
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gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1) |
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gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1)));
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}
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int gr_tu104_get_offset_in_gpccs_segment(struct gk20a *g,
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enum ctxsw_addr_type addr_type,
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u32 num_tpcs,
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u32 num_ppcs,
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u32 reg_list_ppc_count,
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u32 *__offset_in_segment)
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{
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u32 offset_in_segment = 0;
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u32 num_pes_per_gpc = nvgpu_get_litter_value(g,
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GPU_LIT_NUM_PES_PER_GPC);
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if (addr_type == CTXSW_ADDR_TYPE_TPC) {
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/*
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* reg = g->netlist_vars->ctxsw_regs.tpc.l;
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* offset_in_segment = 0;
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*/
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} else if (addr_type == CTXSW_ADDR_TYPE_PPC) {
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/*
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* The ucode stores TPC data before PPC data.
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* Advance offset past TPC data to PPC data.
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*/
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offset_in_segment =
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((g->netlist_vars->ctxsw_regs.tpc.count *
|
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num_tpcs) << 2);
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} else if (addr_type == CTXSW_ADDR_TYPE_GPC) {
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/*
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* The ucode stores TPC/PPC data before GPC data.
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* Advance offset past TPC/PPC data to GPC data.
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*
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* Note 1 PES_PER_GPC case
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*/
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if (num_pes_per_gpc > 1U) {
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offset_in_segment =
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(((g->netlist_vars->ctxsw_regs.tpc.count *
|
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num_tpcs) << 2) +
|
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((reg_list_ppc_count * num_ppcs) << 2));
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||||
} else {
|
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offset_in_segment =
|
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((g->netlist_vars->ctxsw_regs.tpc.count *
|
||||
num_tpcs) << 2);
|
||||
}
|
||||
} else if ((addr_type == CTXSW_ADDR_TYPE_EGPC) ||
|
||||
(addr_type == CTXSW_ADDR_TYPE_ETPC)) {
|
||||
if (num_pes_per_gpc > 1U) {
|
||||
offset_in_segment =
|
||||
((g->netlist_vars->ctxsw_regs.tpc.count *
|
||||
num_tpcs) << 2) +
|
||||
((reg_list_ppc_count * num_ppcs) << 2) +
|
||||
(g->netlist_vars->ctxsw_regs.gpc.count << 2);
|
||||
} else {
|
||||
offset_in_segment =
|
||||
((g->netlist_vars->ctxsw_regs.tpc.count *
|
||||
num_tpcs) << 2) +
|
||||
(g->netlist_vars->ctxsw_regs.gpc.count << 2);
|
||||
}
|
||||
|
||||
/* aligned to next 256 byte */
|
||||
offset_in_segment = ALIGN(offset_in_segment, 256);
|
||||
|
||||
nvgpu_log(g, gpu_dbg_info | gpu_dbg_gpu_dbg,
|
||||
"egpc etpc offset_in_segment 0x%#08x",
|
||||
offset_in_segment);
|
||||
} else {
|
||||
nvgpu_log_fn(g, "Unknown address type.");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*__offset_in_segment = offset_in_segment;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gr_tu104_set_sm_disp_ctrl(struct gk20a *g, u32 data)
|
||||
{
|
||||
u32 reg_val;
|
||||
|
||||
nvgpu_log_fn(g, " ");
|
||||
|
||||
reg_val = nvgpu_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
|
||||
|
||||
if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK)
|
||||
== NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_DISABLE) {
|
||||
reg_val = set_field(reg_val,
|
||||
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(),
|
||||
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f()
|
||||
);
|
||||
} else if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK)
|
||||
== NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE) {
|
||||
reg_val = set_field(reg_val,
|
||||
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(),
|
||||
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f()
|
||||
);
|
||||
}
|
||||
|
||||
nvgpu_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), reg_val);
|
||||
}
|
||||
|
||||
int gr_tu104_handle_sw_method(struct gk20a *g, u32 addr,
|
||||
u32 class_num, u32 offset, u32 data)
|
||||
{
|
||||
nvgpu_log_fn(g, " ");
|
||||
|
||||
if (class_num == TURING_COMPUTE_A) {
|
||||
switch (offset << 2) {
|
||||
case NVC5C0_SET_SHADER_EXCEPTIONS:
|
||||
gv11b_gr_set_shader_exceptions(g, data);
|
||||
break;
|
||||
case NVC5C0_SET_SKEDCHECK:
|
||||
gr_gv11b_set_skedcheck(g, data);
|
||||
break;
|
||||
case NVC5C0_SET_SM_DISP_CTRL:
|
||||
gr_tu104_set_sm_disp_ctrl(g, data);
|
||||
break;
|
||||
case NVC5C0_SET_SHADER_CUT_COLLECTOR:
|
||||
gr_gv11b_set_shader_cut_collector(g, data);
|
||||
break;
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
if (class_num == TURING_A) {
|
||||
switch (offset << 2) {
|
||||
case NVC597_SET_SHADER_EXCEPTIONS:
|
||||
gv11b_gr_set_shader_exceptions(g, data);
|
||||
break;
|
||||
case NVC597_SET_CIRCULAR_BUFFER_SIZE:
|
||||
g->ops.gr.set_circular_buffer_size(g, data);
|
||||
break;
|
||||
case NVC597_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
|
||||
g->ops.gr.set_alpha_circular_buffer_size(g, data);
|
||||
break;
|
||||
case NVC597_SET_GO_IDLE_TIMEOUT:
|
||||
gr_gv11b_set_go_idle_timeout(g, data);
|
||||
break;
|
||||
case NVC097_SET_COALESCE_BUFFER_SIZE:
|
||||
gr_gv11b_set_coalesce_buffer_size(g, data);
|
||||
break;
|
||||
case NVC597_SET_TEX_IN_DBG:
|
||||
gr_gv11b_set_tex_in_dbg(g, data);
|
||||
break;
|
||||
case NVC597_SET_SKEDCHECK:
|
||||
gr_gv11b_set_skedcheck(g, data);
|
||||
break;
|
||||
case NVC597_SET_BES_CROP_DEBUG3:
|
||||
g->ops.gr.set_bes_crop_debug3(g, data);
|
||||
break;
|
||||
case NVC597_SET_BES_CROP_DEBUG4:
|
||||
g->ops.gr.set_bes_crop_debug4(g, data);
|
||||
break;
|
||||
case NVC597_SET_SM_DISP_CTRL:
|
||||
gr_tu104_set_sm_disp_ctrl(g, data);
|
||||
break;
|
||||
case NVC597_SET_SHADER_CUT_COLLECTOR:
|
||||
gr_gv11b_set_shader_cut_collector(g, data);
|
||||
break;
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void gr_tu104_init_sm_dsm_reg_info(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
void gr_tu104_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
|
||||
u32 *num_sm_dsm_perf_ctrl_regs,
|
||||
u32 **sm_dsm_perf_ctrl_regs,
|
||||
u32 *ctrl_register_stride)
|
||||
{
|
||||
*num_sm_dsm_perf_ctrl_regs = 0;
|
||||
*sm_dsm_perf_ctrl_regs = NULL;
|
||||
*ctrl_register_stride = 0;
|
||||
}
|
||||
>>>>>>> CHANGE (f0762e gpu: nvgpu: add speculative barrier)
|
||||
Reference in New Issue
Block a user