gpu: nvgpu: enable Orin support in safety build

Most of the Orin chip specific code is compiled out of safety build
with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the
config protection from Orin/GA10B specific code. Currently all code
is enabled. Code not required in safety will be compiled out later
in separate activity.

Other noteworthy changes in this patch related to safety build:

- In ga10b_ce_request_idle(), add a log print to dump num_pce so that
  compiler does not complain about unused variable num_pce.
- In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and
  recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation
  errors of unused variables.
- Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL
  is GA100 specific and not required for GA10B.
- Compile out gr_ga100_process_context_buffer_priv_segment() with
  CONFIG_NVGPU_DEBUGGER.
- Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA.
- In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable
  with appropriate configs to fix unused variable compilation error.
- In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls
  with CONFIG_NVGPU_POWER_PG.
- In ga10b_pmu_handle_swgen1_irq(), move whole function body under
  CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors.
- Add below TU104 specific files in safety build since some of the code
  in those files is required for GA10B. Unnecessary code will be
  compiled out later on.
	hal/gr/init/gr_init_tu104.c
	hal/class/class_tu104.c
	hal/mc/mc_tu104.c
	hal/fifo/usermode_tu104.c
	hal/gr/falcon/gr_falcon_tu104.c
- Compile out GA10B specific debugger/profiler related files from
  safety build.
- Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily
  to work around compilation errors seen with keeping this config
  enabled. Config will be re-enabled in safety debug build later.

Jira NVGPU-7276

Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/falcon/falcon.c

@@ -29,10 +29,7 @@
 #ifdef CONFIG_NVGPU_DGPU
 #include "falcon_sw_tu104.h"
 #endif
-
-#ifdef CONFIG_NVGPU_NON_FUSA
 #include "falcon_sw_ga10b.h"
-#endif /* CONFIG_NVGPU_NON_FUSA */
 
 #if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
 #include <nvgpu_next_falcon.h>
@@ -394,7 +391,6 @@ u32 nvgpu_falcon_get_id(struct nvgpu_falcon *flcn)
 	return flcn->flcn_id;
 }
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 bool nvgpu_falcon_is_falcon2_enabled(struct nvgpu_falcon *flcn)
 {
 	return flcn->is_falcon2_enabled ? true : false;
@@ -405,7 +401,6 @@ bool nvgpu_falcon_is_feature_supported(struct nvgpu_falcon *flcn,
 {
 	return nvgpu_test_bit(feature, (void *)&flcn->fuse_settings);
 }
-#endif
 
 struct nvgpu_falcon *nvgpu_falcon_get_instance(struct gk20a *g, u32 flcn_id)
 {
@@ -455,9 +450,6 @@ static int falcon_sw_chip_init(struct gk20a *g, struct nvgpu_falcon *flcn)
 	case NVGPU_GPUID_GP10B:
 		gk20a_falcon_sw_init(flcn);
 		break;
-	case NVGPU_GPUID_GA10B:
-		ga10b_falcon_sw_init(flcn);
-		break;
 #ifdef CONFIG_NVGPU_DGPU
 	case NVGPU_GPUID_TU104:
 	case NVGPU_GPUID_GA100:
@@ -465,6 +457,9 @@ static int falcon_sw_chip_init(struct gk20a *g, struct nvgpu_falcon *flcn)
 		break;
 #endif /* CONFIG_NVGPU_DGPU */
 #endif /* CONFIG_NVGPU_NON_FUSA */
+	case NVGPU_GPUID_GA10B:
+		ga10b_falcon_sw_init(flcn);
+		break;
 	case NVGPU_GPUID_GV11B:
 		gk20a_falcon_sw_init(flcn);
 		break;
@@ -561,6 +556,18 @@ void nvgpu_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
 	g->ops.falcon.set_irq(flcn, enable, intr_mask, intr_dest);
 }
 
+int nvgpu_falcon_get_mem_size(struct nvgpu_falcon *flcn,
+			      enum falcon_mem_type type, u32 *size)
+{
+	if (!is_falcon_valid(flcn)) {
+		return -EINVAL;
+	}
+
+	*size = flcn->g->ops.falcon.get_mem_size(flcn, type);
+
+	return 0;
+}
+
 #ifdef CONFIG_NVGPU_DGPU
 int nvgpu_falcon_copy_from_emem(struct nvgpu_falcon *flcn,
 	u32 src, u8 *dst, u32 size, u8 port)
@@ -642,18 +649,6 @@ int nvgpu_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
 	return 0;
 }
 
-int nvgpu_falcon_get_mem_size(struct nvgpu_falcon *flcn,
-			      enum falcon_mem_type type, u32 *size)
-{
-	if (!is_falcon_valid(flcn)) {
-		return -EINVAL;
-	}
-
-	*size = flcn->g->ops.falcon.get_mem_size(flcn, type);
-
-	return 0;
-}
-
 int nvgpu_falcon_clear_halt_intr_status(struct nvgpu_falcon *flcn,
 	unsigned int timeout)
 {