gpu: nvgpu: enable Orin support in safety build

Most of the Orin chip specific code is compiled out of safety build
with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the
config protection from Orin/GA10B specific code. Currently all code
is enabled. Code not required in safety will be compiled out later
in separate activity.

Other noteworthy changes in this patch related to safety build:

- In ga10b_ce_request_idle(), add a log print to dump num_pce so that
  compiler does not complain about unused variable num_pce.
- In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and
  recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation
  errors of unused variables.
- Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL
  is GA100 specific and not required for GA10B.
- Compile out gr_ga100_process_context_buffer_priv_segment() with
  CONFIG_NVGPU_DEBUGGER.
- Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA.
- In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable
  with appropriate configs to fix unused variable compilation error.
- In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls
  with CONFIG_NVGPU_POWER_PG.
- In ga10b_pmu_handle_swgen1_irq(), move whole function body under
  CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors.
- Add below TU104 specific files in safety build since some of the code
  in those files is required for GA10B. Unnecessary code will be
  compiled out later on.
	hal/gr/init/gr_init_tu104.c
	hal/class/class_tu104.c
	hal/mc/mc_tu104.c
	hal/fifo/usermode_tu104.c
	hal/gr/falcon/gr_falcon_tu104.c
- Compile out GA10B specific debugger/profiler related files from
  safety build.
- Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily
  to work around compilation errors seen with keeping this config
  enabled. Config will be re-enabled in safety debug build later.

Jira NVGPU-7276

Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/gr/gr.c

@@ -223,11 +223,9 @@ static int gr_init_setup_hw(struct gk20a *g, struct nvgpu_gr *gr)
 
 	nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.gr.init.eng_config != NULL) {
 		g->ops.gr.init.eng_config(g);
 	}
-#endif
 
 	g->ops.gr.init.gpc_mmu(g);
 
@@ -565,10 +563,8 @@ static int gr_init_prepare_hw_impl(struct gk20a *g)
 			sw_non_ctx_load->l[i].value);
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	nvgpu_gr_init_reset_enable_hw_non_ctx_local(g);
 	nvgpu_gr_init_reset_enable_hw_non_ctx_global(g);
-#endif
 	nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes");
 
 	err = g->ops.gr.falcon.wait_mem_scrubbing(g);
@@ -621,7 +617,6 @@ static int gr_reset_engine(struct gk20a *g)
 		return err;
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	if (g->ops.gr.init.reset_gpcs != NULL) {
 		err = g->ops.gr.init.reset_gpcs(g);
 		if (err != 0) {
@@ -629,7 +624,6 @@ static int gr_reset_engine(struct gk20a *g)
 			return err;
 		}
 	}
-#endif
 
 	err = g->ops.mc.enable_dev(g, dev, true);
 	if (err != 0) {
@@ -797,7 +791,6 @@ int nvgpu_gr_reset(struct gk20a *g)
 }
 #endif
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 static int gr_init_sm_id_config_early(struct gk20a *g, struct nvgpu_gr *gr)
 {
 	int err;
@@ -811,7 +804,6 @@ static int gr_init_sm_id_config_early(struct gk20a *g, struct nvgpu_gr *gr)
 
 	return 0;
 }
-#endif
 
 static int gr_init_ctxsw_falcon_support(struct gk20a *g, struct nvgpu_gr *gr)
 {
@@ -853,7 +845,6 @@ static int gr_init_support_impl(struct gk20a *g)
 		}
 	}
 
-#if defined(CONFIG_NVGPU_NON_FUSA)
 	/*
 	 * Move sm id programming before loading ctxsw and gpccs firmwares. This
 	 * is the actual sequence expected by ctxsw ucode.
@@ -862,7 +853,6 @@ static int gr_init_support_impl(struct gk20a *g)
 	if (err != 0) {
 		return err;
 	}
-#endif
 
 	err = gr_init_ctxsw_falcon_support(g, gr);
 	if (err != 0) {
@@ -1214,7 +1204,6 @@ u32 nvgpu_gr_get_tpc_num(struct gk20a *g, u32 addr)
 	return 0;
 }
 
-#ifdef CONFIG_NVGPU_NON_FUSA
 void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g)
 {
 	u32 i = 0U;
@@ -1268,4 +1257,3 @@ void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g)
 
 	return;
 }
-#endif