nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 02:22:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add chip specific ECC counters

Browse Source 
Add support for ECC counters for HUB MMU

JIRA: GPUT19X-82

Change-Id: I691d5898d4db9fe2cd68f217baa646479ab5cb00
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1490825
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
David Nieto
2017-05-26 14:36:26 -07:00
committed by mobile promotions
parent 345eaef6a7
commit 3dc28cb1ab
4 changed files with 513 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/nvgpu/gv11b/ecc_gv11b.h
View File

@@ -40,4 +40,16 @@ struct ecc_ltc_t19x {
struct gk20a_ecc_stat l2_cache_uncorrected_err_count;
};
/* TODO: PMU and FB ECC features are still under embargo */
struct ecc_eng_t19x {
/* FB */
struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count;
struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count;
struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count;
struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count;
struct gk20a_ecc_stat mmu_fillunit_corrected_err_count;
struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count;
/* PMU */
};
#endif

203
drivers/gpu/nvgpu/gv11b/fb_gv11b.c
View File

@@ -224,6 +224,185 @@ void gv11b_fb_disable_hub_intr(struct gk20a *g,
gv11b_fb_intr_en_clr(g, index, mask);
}
static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status)
{
u32 ecc_addr, corrected_cnt, uncorrected_cnt;
u32 corrected_delta, uncorrected_delta;
u32 corrected_overflow, uncorrected_overflow;
ecc_addr = gk20a_readl(g, fb_mmu_l2tlb_ecc_address_r());
corrected_cnt = gk20a_readl(g,
fb_mmu_l2tlb_ecc_corrected_err_count_r());
uncorrected_cnt = gk20a_readl(g,
fb_mmu_l2tlb_ecc_uncorrected_err_count_r());
corrected_delta = fb_mmu_l2tlb_ecc_corrected_err_count_total_v(
corrected_cnt);
uncorrected_delta = fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(
uncorrected_cnt);
corrected_overflow = ecc_status &
fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m();
uncorrected_overflow = ecc_status &
fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m();
/* clear the interrupt */
if ((corrected_delta > 0) || corrected_overflow)
gk20a_writel(g, fb_mmu_l2tlb_ecc_corrected_err_count_r(), 0);
if ((uncorrected_delta > 0) || uncorrected_overflow)
gk20a_writel(g, fb_mmu_l2tlb_ecc_uncorrected_err_count_r(), 0);
gk20a_writel(g, fb_mmu_l2tlb_ecc_status_r(),
fb_mmu_l2tlb_ecc_status_reset_clear_f());
/* Handle overflow */
if (corrected_overflow)
corrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_corrected_err_count_total_s());
if (uncorrected_overflow)
uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s());
g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0] +=
corrected_delta;
g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0] +=
uncorrected_delta;
if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m())
nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
if (ecc_status & fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m())
nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
if (corrected_overflow || uncorrected_overflow)
nvgpu_info(g, "mmu l2tlb ecc counter overflow!");
nvgpu_log(g, gpu_dbg_intr,
"ecc error address: 0x%x", ecc_addr);
nvgpu_log(g, gpu_dbg_intr,
"ecc error count corrected: %d, uncorrected %d",
g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0],
g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0]);
}
static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status)
{
u32 ecc_addr, corrected_cnt, uncorrected_cnt;
u32 corrected_delta, uncorrected_delta;
u32 corrected_overflow, uncorrected_overflow;
ecc_addr = gk20a_readl(g, fb_mmu_hubtlb_ecc_address_r());
corrected_cnt = gk20a_readl(g,
fb_mmu_hubtlb_ecc_corrected_err_count_r());
uncorrected_cnt = gk20a_readl(g,
fb_mmu_hubtlb_ecc_uncorrected_err_count_r());
corrected_delta = fb_mmu_hubtlb_ecc_corrected_err_count_total_v(
corrected_cnt);
uncorrected_delta = fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(
uncorrected_cnt);
corrected_overflow = ecc_status &
fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m();
uncorrected_overflow = ecc_status &
fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m();
/* clear the interrupt */
if ((corrected_delta > 0) || corrected_overflow)
gk20a_writel(g, fb_mmu_hubtlb_ecc_corrected_err_count_r(), 0);
if ((uncorrected_delta > 0) || uncorrected_overflow)
gk20a_writel(g, fb_mmu_hubtlb_ecc_uncorrected_err_count_r(), 0);
gk20a_writel(g, fb_mmu_hubtlb_ecc_status_r(),
fb_mmu_hubtlb_ecc_status_reset_clear_f());
/* Handle overflow */
if (corrected_overflow)
corrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_corrected_err_count_total_s());
if (uncorrected_overflow)
uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s());
g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0] +=
corrected_delta;
g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0] +=
uncorrected_delta;
if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m())
nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error");
if (ecc_status & fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m())
nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error");
if (corrected_overflow || uncorrected_overflow)
nvgpu_info(g, "mmu hubtlb ecc counter overflow!");
nvgpu_log(g, gpu_dbg_intr,
"ecc error address: 0x%x", ecc_addr);
nvgpu_log(g, gpu_dbg_intr,
"ecc error count corrected: %d, uncorrected %d",
g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0],
g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0]);
}
static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status)
{
u32 ecc_addr, corrected_cnt, uncorrected_cnt;
u32 corrected_delta, uncorrected_delta;
u32 corrected_overflow, uncorrected_overflow;
ecc_addr = gk20a_readl(g, fb_mmu_fillunit_ecc_address_r());
corrected_cnt = gk20a_readl(g,
fb_mmu_fillunit_ecc_corrected_err_count_r());
uncorrected_cnt = gk20a_readl(g,
fb_mmu_fillunit_ecc_uncorrected_err_count_r());
corrected_delta = fb_mmu_fillunit_ecc_corrected_err_count_total_v(
corrected_cnt);
uncorrected_delta = fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(
uncorrected_cnt);
corrected_overflow = ecc_status &
fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m();
uncorrected_overflow = ecc_status &
fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m();
/* clear the interrupt */
if ((corrected_delta > 0) || corrected_overflow)
gk20a_writel(g, fb_mmu_fillunit_ecc_corrected_err_count_r(), 0);
if ((uncorrected_delta > 0) || uncorrected_overflow)
gk20a_writel(g, fb_mmu_fillunit_ecc_uncorrected_err_count_r(), 0);
gk20a_writel(g, fb_mmu_fillunit_ecc_status_r(),
fb_mmu_fillunit_ecc_status_reset_clear_f());
/* Handle overflow */
if (corrected_overflow)
corrected_delta += (0x1UL << fb_mmu_fillunit_ecc_corrected_err_count_total_s());
if (uncorrected_overflow)
uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s());
g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0] +=
corrected_delta;
g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0] +=
uncorrected_delta;
if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m())
nvgpu_log(g, gpu_dbg_intr, "corrected ecc pte data error");
if (ecc_status & fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m())
nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pte data error");
if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m())
nvgpu_log(g, gpu_dbg_intr, "corrected ecc pde0 data error");
if (ecc_status & fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m())
nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pde0 data error");
if (corrected_overflow || uncorrected_overflow)
nvgpu_info(g, "mmu fillunit ecc counter overflow!");
nvgpu_log(g, gpu_dbg_intr,
"ecc error address: 0x%x", ecc_addr);
nvgpu_log(g, gpu_dbg_intr,
"ecc error count corrected: %d, uncorrected %d",
g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0],
g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0]);
}
static void gv11b_fb_hub_isr(struct gk20a *g)
{
u32 status;
@@ -246,28 +425,16 @@ static void gv11b_fb_hub_isr(struct gk20a *g)
HUB_INTR_TYPE_ECC_UNCORRECTED);
status = gk20a_readl(g, fb_mmu_l2tlb_ecc_status_r());
if (status) {
nvgpu_info(g, "hub mmu L2 ecc status: 0x%x",
status);
gk20a_writel(g, fb_mmu_l2tlb_ecc_status_r(),
fb_mmu_l2tlb_ecc_status_reset_clear_f());
}
if (status)
gv11b_handle_l2tlb_ecc_isr(g, status);
status = gk20a_readl(g, fb_mmu_hubtlb_ecc_status_r());
if (status) {
nvgpu_info(g, "hub mmu hub tlb ecc status: 0x%x",
status);
gk20a_writel(g, fb_mmu_hubtlb_ecc_status_r(),
fb_mmu_hubtlb_ecc_status_reset_clear_f());
}
if (status)
gv11b_handle_hubtlb_ecc_isr(g, status);
status = gk20a_readl(g, fb_mmu_fillunit_ecc_status_r());
if (status) {
nvgpu_info(g, "hub mmu fill unit ecc status: 0x%x",
status);
gk20a_writel(g, fb_mmu_fillunit_ecc_status_r(),
fb_mmu_fillunit_ecc_status_reset_clear_f());
}
if (status)
gv11b_handle_fillunit_ecc_isr(g, status);
/* re-enable interrupts after handling */
gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX,

80
drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
View File

@@ -182,6 +182,13 @@ static struct device_attribute *dev_attr_gpccs_ecc_uncorrected_err_count_array;
static struct device_attribute *dev_attr_l2_cache_ecc_corrected_err_count_array;
static struct device_attribute *dev_attr_l2_cache_ecc_uncorrected_err_count_array;
static struct device_attribute *dev_attr_mmu_l2tlb_ecc_corrected_err_count_array;
static struct device_attribute *dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array;
static struct device_attribute *dev_attr_mmu_hubtlb_ecc_corrected_err_count_array;
static struct device_attribute *dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array;
static struct device_attribute *dev_attr_mmu_fillunit_ecc_corrected_err_count_array;
static struct device_attribute *dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array;
void gr_gv11b_create_sysfs(struct device *dev)
{
struct gk20a *g = get_gk20a(dev);
@@ -310,6 +317,49 @@ void gr_gv11b_create_sysfs(struct device *dev)
"mmu_l1tlb_ecc_corrected_err_count",
&g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count,
dev_attr_mmu_l1tlb_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
1,
"eng",
"mmu_l2tlb_ecc_uncorrected_err_count",
&g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count,
dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
1,
"eng",
"mmu_l2tlb_ecc_corrected_err_count",
&g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count,
dev_attr_mmu_l2tlb_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
1,
"eng",
"mmu_hubtlb_ecc_uncorrected_err_count",
&g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count,
dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
1,
"eng",
"mmu_hubtlb_ecc_corrected_err_count",
&g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count,
dev_attr_mmu_hubtlb_ecc_corrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
1,
"eng",
"mmu_fillunit_ecc_uncorrected_err_count",
&g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count,
dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array);
error |= gp10b_ecc_stat_create(dev,
1,
"eng",
"mmu_fillunit_ecc_corrected_err_count",
&g->ecc.eng.t19x.mmu_fillunit_corrected_err_count,
dev_attr_mmu_fillunit_ecc_corrected_err_count_array);
if (error)
dev_err(dev, "Failed to create gv11b sysfs attributes!\n");
}
@@ -407,4 +457,34 @@ static void gr_gv11b_remove_sysfs(struct device *dev)
g->gr.gpc_count,
&g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count,
dev_attr_mmu_l1tlb_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count,
dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count,
dev_attr_mmu_l2tlb_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count,
dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count,
dev_attr_mmu_hubtlb_ecc_corrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count,
dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array);
gp10b_ecc_stat_remove(dev,
1,
&g->ecc.eng.t19x.mmu_fillunit_corrected_err_count,
dev_attr_mmu_fillunit_ecc_corrected_err_count_array);
}

236
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
View File

@@ -466,6 +466,22 @@ static inline u32 fb_mmu_l2tlb_ecc_status_r(void)
{
return 0x00100e70;
}
static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void)
{
return 0x1 << 0;
}
static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void)
{
return 0x1 << 1;
}
static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void)
{
return 0x1 << 16;
}
static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void)
{
return 0x1 << 18;
}
static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v)
{
return (v & 0x1) << 30;
@@ -474,10 +490,86 @@ static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void)
{
return 0x40000000;
}
static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void)
{
return 0x00100e74;
}
static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void)
{
return 16;
}
static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void)
{
return 0xffff << 0;
}
static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void)
{
return 0x00100e78;
}
static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void)
{
return 16;
}
static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void)
{
return 0xffff << 0;
}
static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 fb_mmu_l2tlb_ecc_address_r(void)
{
return 0x00100e7c;
}
static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void)
{
return 32;
}
static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void)
{
return 0xffffffff << 0;
}
static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 fb_mmu_hubtlb_ecc_status_r(void)
{
return 0x00100e84;
}
static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void)
{
return 0x1 << 0;
}
static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void)
{
return 0x1 << 1;
}
static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void)
{
return 0x1 << 16;
}
static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void)
{
return 0x1 << 18;
}
static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v)
{
return (v & 0x1) << 30;
@@ -486,10 +578,94 @@ static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void)
{
return 0x40000000;
}
static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void)
{
return 0x00100e88;
}
static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void)
{
return 16;
}
static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void)
{
return 0xffff << 0;
}
static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void)
{
return 0x00100e8c;
}
static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void)
{
return 16;
}
static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void)
{
return 0xffff << 0;
}
static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 fb_mmu_hubtlb_ecc_address_r(void)
{
return 0x00100e90;
}
static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void)
{
return 32;
}
static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void)
{
return 0xffffffff << 0;
}
static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 fb_mmu_fillunit_ecc_status_r(void)
{
return 0x00100e98;
}
static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void)
{
return 0x1 << 0;
}
static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void)
{
return 0x1 << 1;
}
static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void)
{
return 0x1 << 2;
}
static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void)
{
return 0x1 << 3;
}
static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void)
{
return 0x1 << 16;
}
static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void)
{
return 0x1 << 18;
}
static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v)
{
return (v & 0x1) << 30;
@@ -498,6 +674,66 @@ static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void)
{
return 0x40000000;
}
static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void)
{
return 0x00100e9c;
}
static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void)
{
return 16;
}
static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void)
{
return 0xffff << 0;
}
static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void)
{
return 0x00100ea0;
}
static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void)
{
return 16;
}
static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void)
{
return 0xffff << 0;
}
static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r)
{
return (r >> 0) & 0xffff;
}
static inline u32 fb_mmu_fillunit_ecc_address_r(void)
{
return 0x00100ea4;
}
static inline u32 fb_mmu_fillunit_ecc_address_index_s(void)
{
return 32;
}
static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 fb_mmu_fillunit_ecc_address_index_m(void)
{
return 0xffffffff << 0;
}
static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 fb_niso_flush_sysmem_addr_r(void)
{
return 0x00100c10;