gpu: nvgpu: hal for syncpt_incr_per_release

Create hal to indicate syncpt increments per release.
Legacy chip uses 2 syncpt increments per release and gv1xx
onwards uses 1 syncpt increment per release.

Bug 2066025

Change-Id: I5d6d0a5368ef561f8150fbb7120181f49f6e338b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1669817
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c

@@ -1,7 +1,7 @@
 /*
  * GK20A Channel Synchronization Abstraction
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -194,7 +194,8 @@ static int __gk20a_channel_syncpt_incr(struct gk20a_channel_sync *s,
 	c->g->ops.fifo.add_syncpt_incr_cmd(c->g, wfi_cmd,
 			incr_cmd, sp->id, sp->syncpt_buf.gpu_va);
 
-	thresh = nvgpu_nvhost_syncpt_incr_max_ext(sp->nvhost_dev, sp->id, 2);
+	thresh = nvgpu_nvhost_syncpt_incr_max_ext(sp->nvhost_dev, sp->id,
+			c->g->ops.fifo.get_syncpt_incr_per_release());
 
 	if (register_irq) {
 		struct channel_gk20a *referenced = gk20a_channel_get(c);

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -3999,6 +3999,11 @@ u32 gk20a_fifo_get_syncpt_wait_cmd_size(void)
 	return 4;
 }
 
+u32 gk20a_fifo_get_syncpt_incr_per_release(void)
+{
+	return 2;
+}
+
 void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g,
 		bool wfi_cmd, struct priv_cmd_entry *cmd,
 		u32 id, u64 gpu_va)

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -406,6 +406,7 @@ void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g,
 			struct priv_cmd_entry *cmd, u32 off,
 			u32 id, u32 thresh, u64 gpu_va);
 u32 gk20a_fifo_get_syncpt_wait_cmd_size(void);
+u32 gk20a_fifo_get_syncpt_incr_per_release(void);
 void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g,
 			bool wfi_cmd, struct priv_cmd_entry *cmd,
 			u32 id, u64 gpu_va);

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -631,6 +631,7 @@ struct gpu_ops {
 		u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd);
 		int (*get_sync_ro_map)(struct vm_gk20a *vm,
 				u64 *base_gpuva, u32 *sync_size);
+		u32 (*get_syncpt_incr_per_release)(void);
 #endif
 	} fifo;
 	struct pmu_v {

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -437,6 +437,8 @@ static const struct gpu_ops gm20b_ops = {
 		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
 		.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
+		.get_syncpt_incr_per_release =
+				gk20a_fifo_get_syncpt_incr_per_release,
 		.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
 		.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
 		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -498,6 +498,8 @@ static const struct gpu_ops gp106_ops = {
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
 		.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
 		.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
+		.get_syncpt_incr_per_release =
+				gk20a_fifo_get_syncpt_incr_per_release,
 		.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
 		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
 		.get_sync_ro_map = NULL,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -470,6 +470,8 @@ static const struct gpu_ops gp10b_ops = {
 		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
 		.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
+		.get_syncpt_incr_per_release =
+				gk20a_fifo_get_syncpt_incr_per_release,
 		.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
 		.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
 		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -515,6 +515,8 @@ static const struct gpu_ops gv100_ops = {
 		.get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
 		.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
 		.get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
+		.get_syncpt_incr_per_release =
+                                gv11b_fifo_get_syncpt_incr_per_release,
 		.get_sync_ro_map = gv11b_fifo_get_sync_ro_map,
 #endif
 		.resetup_ramfc = NULL,

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -1779,6 +1779,11 @@ u32 gv11b_fifo_get_syncpt_wait_cmd_size(void)
 	return 8;
 }
 
+u32 gv11b_fifo_get_syncpt_incr_per_release(void)
+{
+	return 1;
+}
+
 void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g,
 		bool wfi_cmd, struct priv_cmd_entry *cmd,
 		u32 id, u64 gpu_va)

drivers/gpu/nvgpu/gv11b/fifo_gv11b.h

@@ -108,6 +108,7 @@ void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g,
 		struct priv_cmd_entry *cmd, u32 off,
 		u32 id, u32 thresh, u64 gpu_va_base);
 u32 gv11b_fifo_get_syncpt_wait_cmd_size(void);
+u32 gv11b_fifo_get_syncpt_incr_per_release(void);
 void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g,
 		bool wfi_cmd, struct priv_cmd_entry *cmd,
 		u32 id, u64 gpu_va_base);

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -531,6 +531,8 @@ static const struct gpu_ops gv11b_ops = {
 		.get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
 		.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
 		.get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
+		.get_syncpt_incr_per_release =
+			gv11b_fifo_get_syncpt_incr_per_release,
 		.get_sync_ro_map = gv11b_fifo_get_sync_ro_map,
 #endif
 		.resetup_ramfc = NULL,

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -347,6 +347,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
 		.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
 		.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
+		.get_syncpt_incr_per_release =
+				gk20a_fifo_get_syncpt_incr_per_release,
 		.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
 		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
 		.get_sync_ro_map = NULL,

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -390,6 +390,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
 		.add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd,
 		.get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size,
+		.get_syncpt_incr_per_release =
+                                gv11b_fifo_get_syncpt_incr_per_release,
 		.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd,
 		.get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size,
 		.get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map,