gpu: nvgpu: add ga10b & ga100 sources

Mass copy ga10b & ga100 sources from nvgpu-next repo. TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1 Jira NVGPU-4771 Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
2025-12-25 02:52:51 +03:00 · 2021-05-04 16:09:51 +05:30
parent 82734765d8
commit 3e43f92f21
326 changed files with 62836 additions and 0 deletions
--- a/drivers/gpu/nvgpu/os/linux/nvlink/hal/ga10b_mssnvlink.c
+++ b/drivers/gpu/nvgpu/os/linux/nvlink/hal/ga10b_mssnvlink.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <nvgpu/log.h>
+#include <nvgpu/enabled.h>
+#include <nvgpu/io.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/soc.h>
+#include <os/linux/module.h>
+#include <os/linux/os_linux.h>
+
+#define MSS_NVLINK_INTERNAL_NUM                 8U
+#define MSS_NVLINK_GLOBAL_CREDIT_CONTROL_0      0x00000010
+#define MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0    0x00000040
+
+#define MSS_NVLINK_SIZE                         0x00001000
+#define MSS_NVLINK_1_BASE                       0x01f20000
+#define MSS_NVLINK_2_BASE                       0x01f40000
+#define MSS_NVLINK_3_BASE                       0x01f60000
+#define MSS_NVLINK_4_BASE                       0x01f80000
+#define MSS_NVLINK_5_BASE                       0x01fa0000
+#define MSS_NVLINK_6_BASE                       0x01fc0000
+#define MSS_NVLINK_7_BASE                       0x01fe0000
+#define MSS_NVLINK_8_BASE                       0x01e00000
+#define MSS_NVLINK_INIT_CREDITS                 0x00000001U
+#define MSS_NVLINK_FORCE_COH_SNP		0x3U
+
+void ga10b_init_nvlink_soc_credits(struct gk20a *g)
+{
+	u32 i = 0U;
+	u32 val = MSS_NVLINK_INIT_CREDITS;
+	struct device *dev = dev_from_gk20a(g);
+
+	u32 nvlink_base[MSS_NVLINK_INTERNAL_NUM] = {
+		MSS_NVLINK_1_BASE, MSS_NVLINK_2_BASE, MSS_NVLINK_3_BASE,
+		MSS_NVLINK_4_BASE, MSS_NVLINK_5_BASE, MSS_NVLINK_6_BASE,
+		MSS_NVLINK_7_BASE, MSS_NVLINK_8_BASE
+	};
+
+	void __iomem *mssnvlink_control[MSS_NVLINK_INTERNAL_NUM];
+
+	if (nvgpu_platform_is_simulation(g)) {
+		nvgpu_log(g, gpu_dbg_info, "simulation platform: "
+			"nvlink soc credits not required");
+		return;
+	}
+
+	if (nvgpu_is_bpmp_running(g) ) {
+		nvgpu_log(g, gpu_dbg_info, "bpmp running: "
+			"nvlink soc credits init done by bpmp");
+		return;
+	}
+	/* init nvlink soc credits and force snoop */
+	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
+		mssnvlink_control[i] = nvgpu_devm_ioremap(dev,
+			nvlink_base[i], MSS_NVLINK_SIZE);
+	}
+
+	nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits");
+
+	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
+		writel_relaxed(val, (*(mssnvlink_control + i) +
+				 MSS_NVLINK_GLOBAL_CREDIT_CONTROL_0));
+	}
+
+	/*
+	 * Set force snoop, always snoop all nvlink memory transactions
+	 * (both coherent and non-coherent)
+	 */
+	nvgpu_log(g, gpu_dbg_info, "set force snoop");
+
+	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
+		val = readl_relaxed((*(mssnvlink_control + i) +
+			MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0));
+		val &= ~(MSS_NVLINK_FORCE_COH_SNP);
+		val |= MSS_NVLINK_FORCE_COH_SNP;
+		writel_relaxed(val, *(mssnvlink_control + i) +
+			MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0);
+	}
+}