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gpu: nvgpu: move gr_gk20a_isr_data struct to gr_intr.h

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Move gr_gk20a_isr_data struct from gr_gk20a.h to
gr_intr.h as nvgpu_gr_isr_data struct.

Update all files that uses the gr_gk20a_isr_data to
nvgpu_gr_isr_data.

JIRA NVGPU-3016

Change-Id: If0ca10a2bbd34f21f430a882403fc7c8a42ec936
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089257
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-03 17:02:36 -07:00
committed by mobile promotions
parent de93ad0d03
commit 3fa094c646
9 changed files with 38 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/gr/gr_intr.c
View File

@@ -50,7 +50,7 @@ static inline bool is_valid_cyclestats_bar0_offset_gk20a(struct gk20a *g,
#endif
int nvgpu_gr_intr_handle_notify_pending(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
struct channel_gk20a *ch = isr_data->ch;
@@ -182,7 +182,7 @@ int nvgpu_gr_intr_handle_notify_pending(struct gk20a *g,
}
int nvgpu_gr_intr_handle_semaphore_pending(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
struct channel_gk20a *ch = isr_data->ch;
struct tsg_gk20a *tsg;

18
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1161,7 +1161,7 @@ int gk20a_gr_reset(struct gk20a *g)
}
static void gk20a_gr_set_error_notifier(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data, u32 error_notifier)
struct nvgpu_gr_isr_data *isr_data, u32 error_notifier)
{
struct channel_gk20a *ch;
struct tsg_gk20a *tsg;
@@ -1181,7 +1181,7 @@ static void gk20a_gr_set_error_notifier(struct gk20a *g,
}
static int gk20a_gr_handle_semaphore_timeout_pending(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
nvgpu_log_fn(g, " ");
gk20a_gr_set_error_notifier(g, isr_data,
@@ -1192,7 +1192,7 @@ static int gk20a_gr_handle_semaphore_timeout_pending(struct gk20a *g,
}
static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
nvgpu_log_fn(g, " ");
gk20a_gr_set_error_notifier(g, isr_data,
@@ -1204,7 +1204,7 @@ static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g,
}
static int gk20a_gr_handle_illegal_method(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
int ret = g->ops.gr.handle_sw_method(g, isr_data->addr,
isr_data->class_num, isr_data->offset,
@@ -1220,7 +1220,7 @@ static int gk20a_gr_handle_illegal_method(struct gk20a *g,
}
static int gk20a_gr_handle_illegal_class(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
nvgpu_log_fn(g, " ");
gk20a_gr_set_error_notifier(g, isr_data,
@@ -1232,7 +1232,7 @@ static int gk20a_gr_handle_illegal_class(struct gk20a *g,
}
int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
int ret = 0;
@@ -1316,7 +1316,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
}
static int gk20a_gr_handle_class_error(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
u32 gr_class_error;
u32 chid = isr_data->ch != NULL ?
@@ -1352,7 +1352,7 @@ static int gk20a_gr_handle_class_error(struct gk20a *g,
}
static int gk20a_gr_handle_firmware_method(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
u32 chid = isr_data->ch != NULL ?
isr_data->ch->chid : FIFO_INVAL_CHANNEL_ID;
@@ -1763,7 +1763,7 @@ static int gk20a_gr_post_bpt_events(struct gk20a *g, struct tsg_gk20a *tsg,
int gk20a_gr_isr(struct gk20a *g)
{
struct gr_gk20a_isr_data isr_data;
struct nvgpu_gr_isr_data isr_data;
u32 obj_table;
bool need_reset = false;
u32 gr_intr = gk20a_readl(g, gr_intr_r());

14
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -57,6 +57,7 @@ struct nvgpu_gr_global_ctx_buffer_desc;
struct nvgpu_gr_global_ctx_local_golden_image;
struct nvgpu_gr_zbc;
struct nvgpu_gr_hwpm_map;
struct nvgpu_gr_isr_data;
enum ctxsw_addr_type;
@@ -108,17 +109,6 @@ struct gk20a_cs_snapshot_client;
struct gk20a_cs_snapshot;
#endif
struct gr_gk20a_isr_data {
u32 addr;
u32 data_lo;
u32 data_hi;
u32 curr_ctx;
struct channel_gk20a *ch;
u32 offset;
u32 sub_chan;
u32 class_num;
};
struct gr_ctx_buffer_desc {
void (*destroy)(struct gk20a *g, struct gr_ctx_buffer_desc *desc);
struct nvgpu_mem mem;
@@ -384,7 +374,7 @@ static inline void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g)
void gr_gk20a_fecs_host_int_enable(struct gk20a *g);
int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
int gk20a_gr_lock_down_sm(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask,
bool check_errors);

3
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -39,6 +39,7 @@
#include <nvgpu/gr/subctx.h>
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_intr.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/obj_ctx.h>
@@ -988,7 +989,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, u32 *__chid)
int gr_gp10b_handle_fecs_error(struct gk20a *g,
struct channel_gk20a *__ch,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
struct channel_gk20a *ch;

4
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -28,7 +28,7 @@
#include "gk20a/mm_gk20a.h"
struct gk20a;
struct gr_gk20a_isr_data;
struct nvgpu_gr_isr_data;
struct nvgpu_gr_ctx;
struct nvgpu_preemption_modes_rec;
struct gk20a_debug_output;
@@ -57,7 +57,7 @@ void gr_gp10b_create_sysfs(struct gk20a *g);
void gr_gp10b_remove_sysfs(struct gk20a *g);
int gr_gp10b_handle_fecs_error(struct gk20a *g,
struct channel_gk20a *__ch,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
struct channel_gk20a *fault_ch);

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1694,7 +1694,7 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr)
int gr_gv11b_handle_fecs_error(struct gk20a *g,
struct channel_gk20a *__ch,
struct gr_gk20a_isr_data *isr_data)
struct nvgpu_gr_isr_data *isr_data)
{
u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
int ret;

4
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -36,7 +36,7 @@ struct nvgpu_gr_ctx;
struct nvgpu_warpstate;
struct nvgpu_tsg_sm_error_state;
struct gr_ctx_desc;
struct gr_gk20a_isr_data;
struct nvgpu_gr_isr_data;
struct gk20a_debug_output;
#define VOLTA_CHANNEL_GPFIFO_A 0xC36FU
@@ -96,7 +96,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
void gr_gv11b_fecs_host_int_enable(struct gk20a *g);
int gr_gv11b_handle_fecs_error(struct gk20a *g,
struct channel_gk20a *__ch,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
int gr_gv11b_init_sw_veid_bundle(struct gk20a *g);
void gr_gv11b_detect_sm_arch(struct gk20a *g);
int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);

7
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -42,6 +42,7 @@ struct nvgpu_netlist_vars;
struct netlist_av_list;
struct nvgpu_gr_global_ctx_buffer_desc;
struct nvgpu_gr_fecs_trace;
struct nvgpu_gr_isr_data;
struct nvgpu_gpu_ctxsw_trace_entry;
struct nvgpu_cpu_time_correlation_sample;
struct nvgpu_mem_sgt;
@@ -343,7 +344,7 @@ struct gpu_ops {
struct nvgpu_warpstate *w_state);
int (*handle_fecs_error)(struct gk20a *g,
struct channel_gk20a *ch,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
int (*pre_process_sm_exception)(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr,
bool sm_debugger_attached,
@@ -776,9 +777,9 @@ struct gpu_ops {
struct {
int (*handle_semaphore_pending)(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
int (*handle_notify_pending)(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
void (*handle_gcc_exception)(struct gk20a *g, u32 gpc,
u32 tpc, u32 gpc_exception,
u32 *corrected_err, u32 *uncorrected_err);

17
drivers/gpu/nvgpu/include/nvgpu/gr/gr_intr.h
View File

@@ -25,7 +25,7 @@
#include <nvgpu/types.h>
struct gr_gk20a_isr_data;
struct channel_gk20a;
struct nvgpu_gr_tpc_exception {
bool tex_exception;
@@ -33,8 +33,19 @@ struct nvgpu_gr_tpc_exception {
bool mpc_exception;
};
struct nvgpu_gr_isr_data {
u32 addr;
u32 data_lo;
u32 data_hi;
u32 curr_ctx;
struct channel_gk20a *ch;
u32 offset;
u32 sub_chan;
u32 class_num;
};
int nvgpu_gr_intr_handle_notify_pending(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
int nvgpu_gr_intr_handle_semaphore_pending(struct gk20a *g,
struct gr_gk20a_isr_data *isr_data);
struct nvgpu_gr_isr_data *isr_data);
#endif /* NVGPU_GR_INTR_H */