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gpu: nvgpu: Fix NS boot transcfg

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Bug 1667322

Accommodate for transcfg address change

Change-Id: I7054202b8ce3be1a3fbfe0465e662be6f9740eb3
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/780326
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Supriya
2015-08-07 12:32:32 +05:30
committed by Terje Bergstrom
parent e44e67333b
commit 3fba1e929b
5 changed files with 41 additions and 6 deletions
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1
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -385,6 +385,7 @@ struct gpu_ops {
struct {
int (*prepare_ucode)(struct gk20a *g);
int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g);
int (*pmu_nsbootstrap)(struct pmu_gk20a *pmu);
int (*pmu_setup_elpg)(struct gk20a *g);
int (*init_wpr_region)(struct gk20a *g);
int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask);

10
drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
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@@ -2476,7 +2476,7 @@ static void pmu_handle_pg_buf_config_msg(struct gk20a *g, struct pmu_msg *msg,
static int gk20a_init_pmu_setup_hw1(struct gk20a *g)
{
struct pmu_gk20a *pmu = &g->pmu;
int err;
int err = 0;
gk20a_dbg_fn("");
@@ -2501,12 +2501,9 @@ static int gk20a_init_pmu_setup_hw1(struct gk20a *g)
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_noncoherent_sysmem_f());
/* TBD: load pmu ucode */
err = pmu_bootstrap(pmu);
if (err)
return err;
err = g->ops.pmu.pmu_nsbootstrap(pmu);
return 0;
return err;
}
@@ -2650,6 +2647,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
{
gops->pmu.prepare_ucode = gk20a_prepare_ucode;
gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
gops->pmu.pmu_setup_elpg = NULL;
gops->pmu.init_wpr_region = NULL;
gops->pmu.load_lsfalcon_ucode = NULL;

33
drivers/gpu/nvgpu/gm20b/acr_gm20b.c
View File

@@ -1213,6 +1213,39 @@ static int bl_bootstrap(struct pmu_gk20a *pmu,
return 0;
}
int gm20b_init_nspmu_setup_hw1(struct gk20a *g)
{
struct pmu_gk20a *pmu = &g->pmu;
int err = 0;
gk20a_dbg_fn("");
mutex_lock(&pmu->isr_mutex);
pmu_reset(pmu);
pmu->isr_enabled = true;
mutex_unlock(&pmu->isr_mutex);
/* setup apertures - virtual */
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
pwr_fbif_transcfg_mem_type_virtual_f());
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
pwr_fbif_transcfg_mem_type_virtual_f());
/* setup apertures - physical */
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_local_fb_f());
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_coherent_sysmem_f());
gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
pwr_fbif_transcfg_mem_type_physical_f() |
pwr_fbif_transcfg_target_noncoherent_sysmem_f());
err = g->ops.pmu.pmu_nsbootstrap(pmu);
return err;
}
static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
struct flcn_bl_dmem_desc *desc, u32 bl_sz)
{

1
drivers/gpu/nvgpu/gm20b/acr_gm20b.h
View File

@@ -407,4 +407,5 @@ int gm20b_pmu_setup_sw(struct gk20a *g);
int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt);
int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_us);
int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
#endif /*__ACR_GM20B_H_*/

2
drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
View File

@@ -291,6 +291,8 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
} else {
gk20a_init_pmu_ops(gops);
gops->pmu.pmu_setup_hw_and_bootstrap =
gm20b_init_nspmu_setup_hw1;
gops->pmu.load_lsfalcon_ucode = NULL;
gops->pmu.init_wpr_region = NULL;
}