gpu: nvgpu: Remove Linux headers from mm_gk20a.h

Delte the Linux headers and make some modifications to get rid of the
minor compilation issues that resulted.

  - Add <linux/iommu.h> to os_linux.h
  - Delete #if 0 code that "flushed" a buffer in gr_gk20a.c
  - Delete FLUSH_CPU_DCACHE() macro
  - Move the cache flush definitions to <nvgpu/linux/vm.h>
    and include this header in sim_gk20a.c. This file will
    not be used by QNX so this should be fine.
  - Add <linux/pci_ids.h> to gp106/bios_gp106.c and
    gp106/mclk_gp106.c.
  - Move function to common/linux/dmabuf.h since it is a
    dmabuf related function and uses a struct device pointer
    as an argument.

JIRA NVGPU-30

Change-Id: I11f56b98524c7fac3efa91b4686592130e5f8a46
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585510
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/linux/dmabuf.h

@@ -70,4 +70,7 @@ int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev);
 int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g,
 			   u64 offset, struct gk20a_buffer_state **state);
 
+int gk20a_mm_get_buffer_info(struct device *dev, int dmabuf_fd,
+			     u64 *buffer_id, u64 *buffer_len);
+
 #endif

drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c

@@ -43,6 +43,7 @@
 #include "gk20a/fence_gk20a.h"
 
 #include "os_linux.h"
+#include "dmabuf.h"
 
 #define HZ_TO_MHZ(a) ((a > 0xF414F9CD7ULL) ? 0xffff : (a >> 32) ? \
 	(u32) ((a * 0x10C8ULL) >> 32) : (u16) ((u32) a/MHZ))

drivers/gpu/nvgpu/common/linux/os_linux.h

@@ -13,10 +13,12 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+
 #ifndef NVGPU_OS_LINUX_H
 #define NVGPU_OS_LINUX_H
 
 #include <linux/cdev.h>
+#include <linux/iommu.h>
 
 #ifdef CONFIG_TEGRA_19x_GPU
 #include <nvgpu/linux/os_linux_t19x.h>

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -7980,14 +7980,6 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
 			ctx_op_nr++;
 		}
 	}
-#if 0
-	/* flush cpu caches for the ctx buffer? only if cpu cached, of course.
-	 * they aren't, yet */
-	if (cached) {
-		FLUSH_CPU_DCACHE(ctx_ptr,
-			 sg_phys(ch_ctx->gr_ctx.mem.ref), size);
-	}
-#endif
 
  cleanup:
 	if (offsets)

drivers/gpu/nvgpu/gk20a/mm_gk20a.h

@@ -21,14 +21,10 @@
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  */
+
 #ifndef MM_GK20A_H
 #define MM_GK20A_H
 
-#include <linux/scatterlist.h>
-#include <linux/iommu.h>
-#include <asm/dma-iommu.h>
-#include <asm/cacheflush.h>
-
 #include <nvgpu/nvgpu_mem.h>
 #include <nvgpu/allocator.h>
 #include <nvgpu/vm.h>
@@ -36,17 +32,6 @@
 #include <nvgpu/rbtree.h>
 #include <nvgpu/kref.h>
 
-#ifdef CONFIG_ARM64
-#define outer_flush_range(a, b)
-#define __cpuc_flush_dcache_area __flush_dcache_area
-#endif
-
-#define FLUSH_CPU_DCACHE(va, pa, size)	\
-	do {	\
-		__cpuc_flush_dcache_area((void *)(va), (size_t)(size));	\
-		outer_flush_range(pa, pa + (size_t)(size));		\
-	} while (0)
-
 struct gpfifo_desc {
 	struct nvgpu_mem mem;
 	u32 entry_num;
@@ -198,7 +183,4 @@ void gk20a_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *mem,
 extern const struct gk20a_mmu_level gk20a_mm_levels_64k[];
 extern const struct gk20a_mmu_level gk20a_mm_levels_128k[];
 
-int gk20a_mm_get_buffer_info(struct device *dev, int dmabuf_fd,
-			     u64 *buffer_id, u64 *buffer_len);
-
 #endif /* MM_GK20A_H */

drivers/gpu/nvgpu/gk20a/sim_gk20a.c

@@ -24,11 +24,12 @@
 #include <linux/highmem.h>
 #include <linux/platform_device.h>
 
+#include <nvgpu/log.h>
+#include <nvgpu/linux/vm.h>
+
 #include "gk20a.h"
 #include "platform_gk20a.h"
 
-#include <nvgpu/log.h>
-
 #include <nvgpu/hw/gk20a/hw_sim_gk20a.h>
 
 static inline void sim_writel(struct gk20a *g, u32 r, u32 v)

drivers/gpu/nvgpu/gp106/bios_gp106.c

@@ -20,6 +20,8 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include <linux/pci_ids.h>
+
 #include <nvgpu/bios.h>
 #include <nvgpu/kmem.h>
 #include <nvgpu/nvgpu_common.h>
@@ -248,4 +250,3 @@ free_firmware:
 		nvgpu_vfree(g, g->bios.data);
 	return err;
 }
-

drivers/gpu/nvgpu/gp106/mclk_gp106.c

@@ -21,6 +21,7 @@
  */
 
 #include <linux/delay.h>
+#include <linux/pci_ids.h>
 
 #include <nvgpu/bios.h>
 #include <nvgpu/kmem.h>

drivers/gpu/nvgpu/include/nvgpu/linux/vm.h

@@ -19,6 +19,18 @@
 
 #include <nvgpu/types.h>
 
+#include <asm/cacheflush.h>
+
+/*
+ * Couple of places explicitly flush caches still. Any DMA buffer we allocate
+ * from within the GPU is writecombine and as a result does not need this but
+ * there seem to be exceptions.
+ */
+#ifdef CONFIG_ARM64
+#define outer_flush_range(a, b)
+#define __cpuc_flush_dcache_area __flush_dcache_area
+#endif
+
 struct sg_table;
 struct dma_buf;