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gpu: nvgpu: Update CE Intr code as per Orin HSIs

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Below CE interrupts do not have any users(usecases) on safety build;
disable them only on safety build.
   1. BLOCKPIPE stall intr: Not used by GFX(VKSC) and CUDA on safety.
   2. NONBLOCK_PIPE nonstall intr: Non-stall intrs are not supported
          on safety build. Also, this one is not used by GFX(VKSC)
          and CUDA.
   3. STALLING_DEBUG intr: Added in Orin tree. It is only needed for
          debugging. Disable on safety build as there is no current
          usage in driver.
   4. POISON_ERROR intr: Poison is a fault containment and not
	  supported on GA10b.
   5. INVALID_CONFIG intr: Floor sweeping not supported on functional
          safety SKU.

Bug 3548082

Change-Id: I8d97ccb38f138b2c04a780e1c255a64d28723405
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671927
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2022-02-18 02:31:07 +00:00
committed by mobile promotions
parent 585c3ab1c1
commit 3fe70bf86e
28 changed files with 170 additions and 165 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
userspace/required_tests.ini
View File

@@ -98,7 +98,6 @@ test_init_hw.bus_init_hw=0
[ce]
test_ce_free_env.ce_free_env=0
test_ce_init_support.ce_init_support=0
test_ce_nonstall_isr.ce_nonstall_isr=0
test_ce_setup_env.ce_setup_env=0
test_ce_stall_isr.ce_stall_isr=0
test_get_num_pce.ce_get_num_pce=0

54
userspace/units/ce/nvgpu-ce.c
View File

@@ -207,7 +207,8 @@ int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args)
g->ops.ce.isr_stall = gv11b_ce_stall_isr;
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
intr_status_written[inst_id] = 0;
intr_val = 0x1f; /* all intr sources */
/* all intr sources except (non)blockpipe as they are not supported on safety */
intr_val = 0x14;
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
g->ops.ce.isr_stall(g, inst_id, 0);
@@ -236,56 +237,6 @@ done:
return ret;
}
int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args)
{
int ret = UNIT_SUCCESS;
int inst_id;
u32 intr_val;
u32 val;
g->ops.ce.isr_nonstall = gp10b_ce_nonstall_isr;
for (inst_id = 0; inst_id < NUM_INST; inst_id++) {
intr_status_written[inst_id] = 0;
intr_val = 0x1f; /* all intr sources */
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
val = g->ops.ce.isr_nonstall(g, inst_id, 0);
if (val != (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
NVGPU_CIC_NONSTALL_OPS_POST_EVENTS)) {
ret = UNIT_FAIL;
unit_err(m, "incorrect ops returned 0x%08x\n", val);
goto done;
}
if (intr_status_written[inst_id] !=
ce_intr_status_nonblockpipe_pending_f()) {
ret = UNIT_FAIL;
unit_err(m, "intr_status not cleared properly, only 0x%08x\n",
intr_status_written[inst_id]);
goto done;
}
intr_status_written[inst_id] = 0;
intr_val = 0x0;
nvgpu_posix_io_writel_reg_space(g, ce_intr_status_r(inst_id),
intr_val);
val = g->ops.ce.isr_nonstall(g, inst_id, 0);
if (val != 0U) {
ret = UNIT_FAIL;
unit_err(m, "incorrect ops returned 0x%08x\n", val);
goto done;
}
if (intr_status_written[inst_id] != intr_val) {
ret = UNIT_FAIL;
unit_err(m, "intr_status not cleared, only 0x%08x\n",
intr_status_written[inst_id]);
goto done;
}
}
done:
return ret;
}
static u32 mock_get_num_lce(struct gk20a *g)
{
return NUM_INST;
@@ -383,7 +334,6 @@ struct unit_module_test ce_tests[] = {
UNIT_TEST(ce_setup_env, test_ce_setup_env, NULL, 0),
UNIT_TEST(ce_init_support, test_ce_init_support, NULL, 0),
UNIT_TEST(ce_stall_isr, test_ce_stall_isr, NULL, 0),
UNIT_TEST(ce_nonstall_isr, test_ce_nonstall_isr, NULL, 0),
UNIT_TEST(mthd_buffer_fault_in_bar2_fault, test_mthd_buffer_fault_in_bar2_fault, NULL, 0),
UNIT_TEST(ce_get_num_pce, test_get_num_pce, NULL, 0),
UNIT_TEST(ce_init_prod_values, test_init_prod_values, NULL, 0),

30
userspace/units/ce/nvgpu-ce.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -115,32 +115,6 @@ int test_ce_init_support(struct unit_module *m, struct gk20a *g, void *args);
*/
int test_ce_stall_isr(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_ce_nonstall_isr
*
* Description: Validate nonstall interrupt handler functionality.
*
* Test Type: Feature
*
* Targets: gops_ce.isr_nonstall, gp10b_ce_nonstall_isr
*
* Input: test_ce_setup_env must have been run.
*
* Steps:
* - Set all CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gops_ce.isr_nonstall.
* - Verify only the nonstall interrupt is cleared and the expected ops are
* returned.
* - Set no CE interrupt sources pending in the interrupt status reg for each
* instance.
* - Call gops_ce.isr_nonstall.
* - Verify no interrupts are cleared and no ops are returned.
*
* Output: Returns PASS if expected result is met, FAIL otherwise.
*/
int test_ce_nonstall_isr(struct unit_module *m, struct gk20a *g, void *args);
/**
* Test specification for: test_mthd_buffer_fault_in_bar2_fault
*
@@ -209,4 +183,4 @@ int test_get_num_pce(struct unit_module *m, struct gk20a *g, void *args);
*/
int test_init_prod_values(struct unit_module *m, struct gk20a *g, void *args);
#endif /* UNIT_NVGPU_CE_H */
#endif /* UNIT_NVGPU_CE_H */

9
userspace/units/mc/nvgpu-mc.c
View File

@@ -176,11 +176,13 @@ static void mock_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
u.ce_isr = true;
}
#ifdef CONFIG_NVGPU_NONSTALL_INTR
static u32 mock_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
{
u.ce_isr = true;
return u.ce_isr_return;
}
#endif
static void mock_fb_isr(struct gk20a *g, u32 intr_unit_bitmask)
{
@@ -254,7 +256,9 @@ int test_mc_setup_env(struct unit_module *m,
/* override HALs */
g->ops.bus.isr = mock_bus_isr;
g->ops.ce.isr_stall = mock_ce_stall_isr;
#ifdef CONFIG_NVGPU_NONSTALL_INTR
g->ops.ce.isr_nonstall = mock_ce_nonstall_isr;
#endif
g->ops.fb.intr.isr = mock_fb_isr;
g->ops.fifo.intr_0_isr = mock_fifo_stall_isr;
g->ops.fifo.intr_1_isr = mock_fifo_nonstall_isr;
@@ -671,15 +675,18 @@ int test_isr_nonstall(struct unit_module *m, struct gk20a *g, void *args)
}
/* for branch coverage set this HAL to NULL */
#ifdef CONFIG_NVGPU_NONSTALL_INTR
g->ops.ce.isr_nonstall = NULL;
#endif
for (i = 0; i < NUM_MC_UNITS; i++) {
intrs_pending |= mc_units[i].bit;
}
nvgpu_posix_io_writel_reg_space(g, NONSTALL_PENDING_REG, intrs_pending);
reset_ctx();
g->ops.mc.isr_nonstall(g);
#ifdef CONFIG_NVGPU_NONSTALL_INTR
g->ops.ce.isr_nonstall = mock_ce_nonstall_isr;
#endif
return UNIT_SUCCESS;
}