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gpu: nvgpu: Update CE Intr code as per Orin HSIs

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Below CE interrupts do not have any users(usecases) on safety build;
disable them only on safety build.
   1. BLOCKPIPE stall intr: Not used by GFX(VKSC) and CUDA on safety.
   2. NONBLOCK_PIPE nonstall intr: Non-stall intrs are not supported
          on safety build. Also, this one is not used by GFX(VKSC)
          and CUDA.
   3. STALLING_DEBUG intr: Added in Orin tree. It is only needed for
          debugging. Disable on safety build as there is no current
          usage in driver.
   4. POISON_ERROR intr: Poison is a fault containment and not
	  supported on GA10b.
   5. INVALID_CONFIG intr: Floor sweeping not supported on functional
          safety SKU.

Bug 3548082

Change-Id: I8d97ccb38f138b2c04a780e1c255a64d28723405
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2671927
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2022-02-18 02:31:07 +00:00
committed by mobile promotions
parent 585c3ab1c1
commit 3fe70bf86e
28 changed files with 170 additions and 165 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
userspace/units/mc/nvgpu-mc.c
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@@ -176,11 +176,13 @@ static void mock_ce_stall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
u.ce_isr = true;
}
#ifdef CONFIG_NVGPU_NONSTALL_INTR
static u32 mock_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
{
u.ce_isr = true;
return u.ce_isr_return;
}
#endif
static void mock_fb_isr(struct gk20a *g, u32 intr_unit_bitmask)
{
@@ -254,7 +256,9 @@ int test_mc_setup_env(struct unit_module *m,
/* override HALs */
g->ops.bus.isr = mock_bus_isr;
g->ops.ce.isr_stall = mock_ce_stall_isr;
#ifdef CONFIG_NVGPU_NONSTALL_INTR
g->ops.ce.isr_nonstall = mock_ce_nonstall_isr;
#endif
g->ops.fb.intr.isr = mock_fb_isr;
g->ops.fifo.intr_0_isr = mock_fifo_stall_isr;
g->ops.fifo.intr_1_isr = mock_fifo_nonstall_isr;
@@ -671,15 +675,18 @@ int test_isr_nonstall(struct unit_module *m, struct gk20a *g, void *args)
}
/* for branch coverage set this HAL to NULL */
#ifdef CONFIG_NVGPU_NONSTALL_INTR
g->ops.ce.isr_nonstall = NULL;
#endif
for (i = 0; i < NUM_MC_UNITS; i++) {
intrs_pending |= mc_units[i].bit;
}
nvgpu_posix_io_writel_reg_space(g, NONSTALL_PENDING_REG, intrs_pending);
reset_ctx();
g->ops.mc.isr_nonstall(g);
#ifdef CONFIG_NVGPU_NONSTALL_INTR
g->ops.ce.isr_nonstall = mock_ce_nonstall_isr;
#endif
return UNIT_SUCCESS;
}