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gpu: nvgpu: remove ops.gr.set_preemption_buffer_va hal

Browse Source 
Add below two new APIs to set preemption buffer in graphics context or
subcontext respectively

nvgpu_gr_ctx_set_preemption_buffer_va()
nvgpu_gr_subctx_set_preemption_buffer_va()

Remove g->ops.gr.set_preemption_buffer_va() hal and use above APIs to
set preemption buffer VA.

Jira NVGPU-1887

Change-Id: I38fb76eaf01d3fc73fd8104f30bcd89be9fa45b6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076272
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-03-18 17:17:53 +05:30
committed by mobile promotions
parent 43c4083bd5
commit 40e63a7857
15 changed files with 42 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/common/gr/ctx.c
View File

@@ -833,3 +833,16 @@ void nvgpu_gr_ctx_set_preemption_modes(struct gk20a *g,
}
}
void nvgpu_gr_ctx_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx)
{
g->ops.gr.ctxsw_prog.set_full_preemption_ptr(g, &gr_ctx->mem,
gr_ctx->preempt_ctxsw_buffer.gpu_va);
if (g->ops.gr.ctxsw_prog.set_full_preemption_ptr_veid0 != NULL) {
g->ops.gr.ctxsw_prog.set_full_preemption_ptr_veid0(g,
&gr_ctx->mem, gr_ctx->preempt_ctxsw_buffer.gpu_va);
}
}

14
drivers/gpu/nvgpu/common/gr/subctx.c
View File

@@ -131,3 +131,17 @@ void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g,
g->ops.gr.ctxsw_prog.set_patch_addr(g, &subctx->ctx_header,
gr_ctx->patch_ctx.mem.gpu_va);
}
void nvgpu_gr_subctx_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx)
{
g->ops.gr.ctxsw_prog.set_full_preemption_ptr(g, &subctx->ctx_header,
gr_ctx->preempt_ctxsw_buffer.gpu_va);
if (g->ops.gr.ctxsw_prog.set_full_preemption_ptr_veid0 != NULL) {
g->ops.gr.ctxsw_prog.set_full_preemption_ptr_veid0(g,
&subctx->ctx_header,
gr_ctx->preempt_ctxsw_buffer.gpu_va);
}
}

1
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -196,7 +196,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.set_boosted_ctx = NULL,
.set_preemption_mode = vgpu_gr_set_preemption_mode,
.pre_process_sm_exception = NULL,
.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
.set_bes_crop_debug3 = NULL,
.set_bes_crop_debug4 = NULL,
.set_ctxsw_preemption_mode =

1
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -214,7 +214,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.set_boosted_ctx = NULL,
.set_preemption_mode = vgpu_gr_set_preemption_mode,
.pre_process_sm_exception = NULL,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.set_bes_crop_debug3 = NULL,
.set_bes_crop_debug4 = NULL,
.set_ctxsw_preemption_mode = vgpu_gr_set_ctxsw_preemption_mode,

21
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -988,7 +988,6 @@ int gr_gp10b_init_ctxsw_preemption_mode(struct gk20a *g,
void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx)
{
struct nvgpu_mem *mem = &gr_ctx->mem;
int err;
nvgpu_log_fn(g, " ");
@@ -1000,15 +999,11 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
u32 size;
u32 cbes_reserve;
if (g->ops.gr.set_preemption_buffer_va != NULL) {
if (subctx != NULL) {
g->ops.gr.set_preemption_buffer_va(g,
&subctx->ctx_header,
gr_ctx->preempt_ctxsw_buffer.gpu_va);
} else {
g->ops.gr.set_preemption_buffer_va(g, mem,
gr_ctx->preempt_ctxsw_buffer.gpu_va);
}
if (subctx != NULL) {
nvgpu_gr_subctx_set_preemption_buffer_va(g, subctx,
gr_ctx);
} else {
nvgpu_gr_ctx_set_preemption_buffer_va(g, gr_ctx);
}
err = nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true);
@@ -2101,12 +2096,6 @@ int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
return 0;
}
void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_mem *mem, u64 gpu_va)
{
g->ops.gr.ctxsw_prog.set_full_preemption_ptr(g, mem, gpu_va);
}
void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g)
{
struct gr_gk20a *gr = &g->gr;

2
drivers/gpu/nvgpu/gp10b/gr_gp10b.h
View File

@@ -127,8 +127,6 @@ int gr_gp10b_get_preemption_mode_flags(struct gk20a *g,
struct nvgpu_preemption_modes_rec *preemption_modes_rec);
int gp10b_gr_fuse_override(struct gk20a *g);
int gr_gp10b_init_preemption_state(struct gk20a *g);
void gr_gp10b_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_mem *mem, u64 gpu_va);
void gr_gp10b_init_gfxp_wfi_timeout_count(struct gk20a *g);
unsigned long gr_gp10b_get_max_gfxp_wfi_timeout_count(struct gk20a *g);
bool gr_gp10b_suspend_context(struct channel_gk20a *ch,

1
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -341,7 +341,6 @@ static const struct gpu_ops gp10b_ops = {
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,
.init_ecc = gp10b_ecc_init,

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -448,7 +448,6 @@ static const struct gpu_ops gv100_ops = {
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
.set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode,

23
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -1506,7 +1506,6 @@ void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data)
void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx, struct nvgpu_gr_subctx *subctx)
{
struct nvgpu_mem *mem = &gr_ctx->mem;
int err;
nvgpu_log_fn(g, " ");
@@ -1518,15 +1517,11 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
u32 size;
u32 cbes_reserve;
if (g->ops.gr.set_preemption_buffer_va != NULL) {
if (subctx != NULL) {
g->ops.gr.set_preemption_buffer_va(g,
&subctx->ctx_header,
gr_ctx->preempt_ctxsw_buffer.gpu_va);
} else {
g->ops.gr.set_preemption_buffer_va(g, mem,
gr_ctx->preempt_ctxsw_buffer.gpu_va);
}
if (subctx != NULL) {
nvgpu_gr_subctx_set_preemption_buffer_va(g, subctx,
gr_ctx);
} else {
nvgpu_gr_ctx_set_preemption_buffer_va(g, gr_ctx);
}
err = nvgpu_gr_ctx_patch_write_begin(g, gr_ctx, true);
@@ -2810,14 +2805,6 @@ void gr_gv11b_load_tpc_mask(struct gk20a *g)
}
void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_mem *mem, u64 gpu_va)
{
/* gpu va still needs to be 8 bit aligned */
g->ops.gr.ctxsw_prog.set_full_preemption_ptr(g, mem, gpu_va);
g->ops.gr.ctxsw_prog.set_full_preemption_ptr_veid0(g, mem, gpu_va);
}
void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel)
{

2
drivers/gpu/nvgpu/gv11b/gr_gv11b.h
View File

@@ -129,8 +129,6 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g,
int gr_gv11b_load_smid_config(struct gk20a *g);
int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va);
void gr_gv11b_load_tpc_mask(struct gk20a *g);
void gr_gv11b_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_mem *mem, u64 gpu_va);
void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel);
int gv11b_gr_sm_trigger_suspend(struct gk20a *g);

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -400,7 +400,6 @@ static const struct gpu_ops gv11b_ops = {
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
.init_ecc = gv11b_ecc_init,

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -435,8 +435,6 @@ struct gpu_ops {
void (*program_zcull_mapping)(struct gk20a *g,
u32 zcull_alloc_num, u32 *zcull_map_tiles);
int (*commit_inst)(struct channel_gk20a *c, u64 gpu_va);
void (*set_preemption_buffer_va)(struct gk20a *g,
struct nvgpu_mem *mem, u64 gpu_va);
void (*load_tpc_mask)(struct gk20a *g);
int (*trigger_suspend)(struct gk20a *g);
int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state);

2
drivers/gpu/nvgpu/include/nvgpu/gr/ctx.h
View File

@@ -222,5 +222,7 @@ bool nvgpu_gr_ctx_check_valid_preemption_mode(struct nvgpu_gr_ctx *gr_ctx,
u32 graphics_preempt_mode, u32 compute_preempt_mode);
void nvgpu_gr_ctx_set_preemption_modes(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx);
void nvgpu_gr_ctx_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_gr_ctx *gr_ctx);
#endif /* NVGPU_INCLUDE_GR_CTX_H */

3
drivers/gpu/nvgpu/include/nvgpu/gr/subctx.h
View File

@@ -52,4 +52,7 @@ void nvgpu_gr_subctx_set_hwpm_mode(struct gk20a *g,
void nvgpu_gr_subctx_set_patch_ctx(struct gk20a *g,
struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx);
void nvgpu_gr_subctx_set_preemption_buffer_va(struct gk20a *g,
struct nvgpu_gr_subctx *subctx, struct nvgpu_gr_ctx *gr_ctx);
#endif /* NVGPU_GR_SUBCTX_H */

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -468,7 +468,6 @@ static const struct gpu_ops tu104_ops = {
.set_boosted_ctx = gr_gp10b_set_boosted_ctx,
.set_preemption_mode = gr_gp10b_set_preemption_mode,
.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception,
.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va,
.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
.set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4,
.init_ecc = tu104_ecc_init,