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gpu: nvgpu: zero blob size support for rail-gating.

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Add support to pass ucode blob size as '0' while
rail-gating.

Bug 200776471

Change-Id: Ib178bc2f8881a1e49c874be346b0e712d4aca923
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2613466
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
mpoojary
2021-10-18 10:26:14 +00:00
committed by mobile promotions
parent 4a7e5056a5
commit 41b7299201
2 changed files with 23 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
View File

@@ -349,16 +349,23 @@ int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr)
struct nvgpu_falcon *flcn = NULL;
flcn = acr->acr_asc.acr_flcn;
err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc);
if (err !=0) {
nvgpu_err(g, "RISCV ucode loading failed");
return -EINVAL;
}
// TODO: Based on Railgating/Cold boot use True/False flag with this call.
err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false);
if (err != 0) {
nvgpu_err(g, "RISCV ucode patch wpr info failed");
return err;
if (acr->acr_asc.manifest_fw != NULL) {
err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, true);
if (err != 0) {
nvgpu_err(g, "RISCV ucode patch wpr info failed");
return err;
}
} else {
err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc);
if (err != 0) {
nvgpu_err(g, "RISCV ucode loading failed");
return -EINVAL;
}
err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false);
if (err != 0) {
nvgpu_err(g, "RISCV ucode patch wpr info failed");
return err;
}
}
acr_sysmem_desc_addr = nvgpu_mem_get_addr(g,
@@ -401,8 +408,9 @@ int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr)
timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout);
return err;
exit:
ga10b_riscv_release_firmware(g, acr);
return err;
}

12
drivers/gpu/nvgpu/common/acr/acr_sw_ga10b.c
View File

@@ -82,14 +82,13 @@ static int ga10b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
/*
* In case of recovery ucode blob size is 0 as it has already
* been authenticated during cold boot.
* TODO: Set blob size as 0x0
* i.e. nonwpr_ucode_blob_size = RECOVERY_UCODE_BLOB_SIZE
* and call with true flag.
*/
if (!nvgpu_mem_is_valid(&acr_desc->acr_falcon2_sysmem_desc)) {
nvgpu_err(g, "invalid mem acr_falcon2_sysmem_desc");
return -EINVAL;
}
acr_sysmem_desc->nonwpr_ucode_blob_size =
RECOVERY_UCODE_BLOB_SIZE;
} else
#endif
{
@@ -107,11 +106,8 @@ static int ga10b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
goto end;
}
} else {
/*
* TODO: Set blob size as 0x0.
* i.e.nonwpr_ucode_blob_size=RECOVERY_UCODE_BLOB_SIZE
* and call with true flag.
*/
acr_sysmem_desc->nonwpr_ucode_blob_size =
RECOVERY_UCODE_BLOB_SIZE;
goto load;
}