nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-25 11:04:51 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Reconcile sim escape paths between RM and nvgpu

Browse Source 
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM.

This is required for igpu to pass on NET21.

Bug 2539889

Change-Id: I5d37ceb799cafb7fc7dec611fda5f5caac7d7f17
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2130414
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Lakshmanan M <lm@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Seshendra Gadagottu
2019-06-04 07:06:51 -07:00
committed by Alex Waterman
parent 85ba7321e7
commit 43324f7b1b
3 changed files with 51 additions and 69 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
drivers/gpu/nvgpu/common/sim/sim.c
View File

@@ -29,7 +29,6 @@
#include <nvgpu/sim.h>
#include <nvgpu/utils.h>
#include <nvgpu/bug.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
int nvgpu_alloc_sim_buffer(struct gk20a *g, struct nvgpu_mem *mem)
@@ -60,32 +59,7 @@ void nvgpu_remove_sim_support(struct gk20a *g)
}
}
static inline u32 sim_msg_header_size(void)
{
return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/
}
static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
{
u8 *cpu_va;
cpu_va = (u8 *)g->sim->msg_bfr.cpu_va;
return (u32 *)(cpu_va + byte_offset);
}
static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
{
return sim_msg_bfr(g, byte_offset); /*starts at 0*/
}
static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
{
/*starts after msg header/cmn*/
return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
}
static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
{
/*memset(g->sim->msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/
*sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v();
@@ -95,11 +69,6 @@ static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
*sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
}
static inline u32 sim_escape_read_hdr_size(void)
{
return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/
}
static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
{
u8 *cpu_va;
@@ -191,7 +160,7 @@ static int rpc_recv_poll(struct gk20a *g)
return 0;
}
static int issue_rpc_and_wait(struct gk20a *g)
int issue_rpc_and_wait(struct gk20a *g)
{
int err;

49
drivers/gpu/nvgpu/common/sim/sim_pci.c
View File

@@ -28,35 +28,20 @@
#include <nvgpu/io.h>
#include <nvgpu/utils.h>
#include <nvgpu/bug.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
static inline u32 sim_msg_header_size(void)
static inline u32 pci_sim_msg_header_size(void)
{
return 32U;
}
static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
{
u8 *cpu_va;
cpu_va = (u8 *)g->sim->msg_bfr.cpu_va;
return (u32 *)(cpu_va + byte_offset);
}
static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
{
return sim_msg_bfr(g, byte_offset); /* starts at 0 */
}
static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
static inline u32 *pci_sim_msg_param(struct gk20a *g, u32 byte_offset)
{
/* starts after msg header/cmn */
return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
return sim_msg_bfr(g, byte_offset + pci_sim_msg_header_size());
}
static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
static inline void pci_sim_write_hdr(struct gk20a *g, u32 func, u32 size)
{
*sim_msg_hdr(g, sim_msg_header_version_r()) =
sim_msg_header_version_major_tot_v() |
@@ -65,12 +50,8 @@ static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size)
*sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v();
*sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v();
*sim_msg_hdr(g, sim_msg_function_r()) = func;
*sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size();
}
static inline u32 sim_escape_read_hdr_size(void)
{
return 12U;
*sim_msg_hdr(g, sim_msg_length_r()) =
size + pci_sim_msg_header_size();
}
static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset)
@@ -160,7 +141,7 @@ static int rpc_recv_poll(struct gk20a *g)
return 0;
}
static int issue_rpc_and_wait(struct gk20a *g)
static int pci_issue_rpc_and_wait(struct gk20a *g)
{
int err;
@@ -191,23 +172,23 @@ static void nvgpu_sim_esc_readl(struct gk20a *g,
size_t pathlen = strlen(path);
u32 data_offset;
sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
pci_sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
sim_escape_read_hdr_size());
*sim_msg_param(g, 0) = index;
*sim_msg_param(g, 4) = sizeof(u32);
*pci_sim_msg_param(g, 0) = index;
*pci_sim_msg_param(g, 4) = sizeof(u32);
data_offset = round_up(pathlen + 1, sizeof(u32));
*sim_msg_param(g, 8) = data_offset + 0xc;
strcpy((char *)sim_msg_param(g, 0xc), path);
*pci_sim_msg_param(g, 8) = data_offset + 0xc;
strcpy((char *)pci_sim_msg_param(g, 0xc), path);
err = issue_rpc_and_wait(g);
err = pci_issue_rpc_and_wait(g);
if (err == 0) {
nvgpu_memcpy((u8 *)data,
(u8 *)sim_msg_param(g, data_offset + 0xc),
(u8 *)pci_sim_msg_param(g, data_offset + 0xc),
sizeof(u32));
} else {
*data = 0xffffffff;
WARN(1, "issue_rpc_and_wait failed err=%d", err);
WARN(1, "pci_issue_rpc_and_wait failed err=%d", err);
}
}

36
drivers/gpu/nvgpu/include/nvgpu/sim.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -25,8 +25,8 @@
#ifdef CONFIG_NVGPU_SIM
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/gk20a.h>
struct gk20a;
struct sim_nvgpu {
struct gk20a *g;
u32 send_ring_put;
@@ -59,6 +59,38 @@ void nvgpu_remove_sim_support(struct gk20a *g);
void sim_writel(struct sim_nvgpu *sim, u32 r, u32 v);
u32 sim_readl(struct sim_nvgpu *sim, u32 r);
int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g);
int issue_rpc_and_wait(struct gk20a *g);
void sim_write_hdr(struct gk20a *g, u32 func, u32 size);
static inline u32 sim_escape_read_hdr_size(void)
{
return 12U; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/
}
static inline u32 sim_msg_header_size(void)
{
return 24U;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/
}
static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset)
{
u8 *cpu_va;
cpu_va = (u8 *)g->sim->msg_bfr.cpu_va;
return (u32 *)(cpu_va + byte_offset);
}
static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset)
{
return sim_msg_bfr(g, byte_offset); /*starts at 0*/
}
static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset)
{
/*starts after msg header/cmn*/
return sim_msg_bfr(g, byte_offset + sim_msg_header_size());
}
#endif
#endif /* NVGPU_SIM_H */