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gpu: nvgpu: use a pointer for ch_state inst mem

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MISRA rule 18.7 doesn't allow flexible array members. To work around
that, modify the instance block member in struct ch_state to be an
explicit pointer and allocate it separately for simplicity.

Jira NVGPU-886

Change-Id: I34299bec79bf7706f9cdfa42dee7fba765c9f312
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928205
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Holtta
2018-10-15 14:49:52 +03:00
committed by mobile promotions
parent 9aa74d5f86
commit 439d3eb74f
3 changed files with 15 additions and 8 deletions
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19
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -4081,7 +4081,7 @@ void gk20a_dump_channel_status_ramfc(struct gk20a *g,
return;
}
inst_mem = &ch_state->inst_block[0];
inst_mem = ch_state->inst_block;
syncpointa = inst_mem[ram_fc_syncpointa_w()];
syncpointb = inst_mem[ram_fc_syncpointb_w()];
@@ -4155,13 +4155,19 @@ void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
for (chid = 0; chid < f->num_channels; chid++) {
struct channel_gk20a *ch = &f->channel[chid];
if (gk20a_channel_get(ch)) {
ch_state[chid] =
nvgpu_kmalloc(g, sizeof(struct ch_state) +
ram_in_alloc_size_v());
struct ch_state *state = nvgpu_kmalloc(g,
sizeof(*state));
u32 *inst = nvgpu_kmalloc(g, ram_in_alloc_size_v());
/* ref taken stays to below loop with
* successful allocs */
if (ch_state[chid] == NULL) {
if (state == NULL || inst == NULL) {
gk20a_channel_put(ch);
nvgpu_kfree(g, state);
nvgpu_kfree(g, inst);
} else {
ch_state[chid] = state;
ch_state[chid]->inst_block = inst;
}
}
}
@@ -4176,7 +4182,7 @@ void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
ch_state[chid]->refs = nvgpu_atomic_read(&ch->ref_count);
ch_state[chid]->deterministic = ch->deterministic;
nvgpu_mem_rd_n(g, &ch->inst_block, 0,
&ch_state[chid]->inst_block[0],
ch_state[chid]->inst_block,
ram_in_alloc_size_v());
gk20a_channel_put(ch);
}
@@ -4184,6 +4190,7 @@ void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
if (ch_state[chid]) {
g->ops.fifo.dump_channel_status_ramfc(g, o, chid,
ch_state[chid]);
nvgpu_kfree(g, ch_state[chid]->inst_block);
nvgpu_kfree(g, ch_state[chid]);
}
}

2
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -221,7 +221,7 @@ struct ch_state {
int pid;
int refs;
bool deterministic;
u32 inst_block[0];
u32 *inst_block;
};
int gk20a_init_fifo_support(struct gk20a *g);

2
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -313,7 +313,7 @@ void gv11b_dump_channel_status_ramfc(struct gk20a *g,
return;
}
inst_mem = &ch_state->inst_block[0];
inst_mem = ch_state->inst_block;
gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d: ", chid,
g->name,